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ams datasheet: 2014-jun-12 [v1-08] AS3911B C 1 AS3911B nfc initiator / hf reader ic the AS3911B is a highly integrated nfc initiator / hf reader ic. it includes the analog front end (afe) and a highly integrated data framing system for iso 18092 (nfcip-1) initiator, iso 18092 (nfcip-1) active target, iso 14443 a and b reader (including high bit rates) and felica? reader. implementation of other standard and custom protocols like mifare? classic 1 is possible through using the afe and im plementing framing in the external microcontroller (stream and transparent modes). compared with concurrent nfc devices designed with the mobile phone in mind, the as39 11b is positioned perfectly for the infrastructure side of the nfc system, where users need optimal rf performance and flexibility combined with low power. with ams unique automatic antenna tuning technology, the device is optimized for applic ations with directly driven antennas. the AS3911B is alone in the domain of hf reader ics in that it contains two differential low impedance (1 ) antenna drivers. the AS3911B includes several features, which make it incomparable for low power applications. it contains a low power capacitive sensor, which can be used to detect the presence of a card without switching on the reader field. additionally, the presence of a card can also be detected by performing a measurement of amplitude or phase of signal on antenna lc tank and comparing it to stored reference. it also contains a low power rc oscillator and wake-up timer, which can be used to wake the system after a defined time period and check for the presence of a tag using one or more techniques of low power detection of card presence (capacitive, phase or amplitude). the AS3911B is designed to operate from a wide power supply range from 2.4 v to 5.5 v; peripheral interface io pins support power supply range from 1.65 v to 5.5 v. ordering information and content guide appear at end of datasheet. 1. mifare? and mifare? classi c are trademarks of nxp b.v general description
AS3911B C 2 ams datasheet: 2014-jun-12 [v1-08] general description key benefits & features the benefits and features of AS3911B, nfc initiator / hf reader ic are listed below: figure 1: added value for AS3911B benefits features nfc active p2p support iso 18092 (nfcip-1) active p2p iso14443 a, b and felica (tm) high data transfer with ask vhbr and fast spi support of vhbr (3.4 mbit/s picc to pcd framing, 6.8 mbit/s afe and pcd to picc framing) 6 a consumption at sensing every 100ms capacitive sensing - wake-up antenna tuning on the fly automatic antenna tuning system providing tuning of antenna lc tank stable modulation index at ask modulati on automatic modulation index adjustment no communication holes am and pm (i/q) demodulator channels with automatic selection high output power for emvco readers up to 1 w in case of differential output high rx sensitivity user selectab le and automatic gain control allows implementation of custom framings transparent and stream modes to implement mifare? classic compliant or other custom protocols multi antenna support possibility of driving two antennas in single ended mode smaller oscillator size oscillator input capable of oper ating with 13.56 mhz or 27.12 mhz crystal with fast start-up easy fifo handling 10 m bit spi with 96 bytes fifo wide supply voltage range from 2.4 v to 5.5 v fits temperature requirements for various applications wide temperature range: -40c to 125c small outline, good cooling through exposed pad qfn 5x5 ld32 package
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 3 general description applications the AS3911B is suitable for a wide range of applications including: ? emv payment ? access control ? nfc infrastructure ?ticketing block diagram the functional blocks of this device for reference are shown below: figure 2: AS3911B block diagram por & bias a/d converter xto xti rfo 1 rfo 2 rfi1 rfi2 vdd csi cso vdd_io AS3911B regulators xtal oscillator rc oscillator a/d converter transmitter phase & amplitude detector receiver external field detector capacitor sensor logic fifo control logic spi interface framing wake-up timer trimx spi level shifters irq mcu_clk por & bias
AS3911B C 4 ams datasheet: 2014-jun-12 [v1-08] pin assignment the AS3911B pin assignments are described below. figure 3: pin diagram figure 4: pin description AS3911B pin assignment: this figure shows the pin assignment and location viewed from top. pin number pin name pin type description 32-pin qfn 1 v dd_io supply pad positive supply for peripheral communication 2 cso analog output capacitor sensor output 3 vsp_d digital supply regulator output 4 xto xtal oscillator output 5xti analog input / digital input xtal oscillator input 6 vsn_d supply pad digital ground 7vsp_a analog output analog supply regulator output 8 v dd supply pad external positive supply pin assignment AS3911B exposed pad 9 25 26 27 28 29 30 31 32 /ss sclk mosi miso mcu_clk irq vsn_a csi 16 15 14 13 12 11 10 vsp_rf rfo1 rfo2 vsn_rf trim1_3 trim2_3 trim1_2 trim2_2 24 23 22 21 20 19 18 17 agd rfi2 rfi1 vss trim2_0 trim1_0 trim2_1 trim1_1 1 2 3 4 5 6 7 8 vdd_io vsp_d cso xto xti vsn_d vsp_a vdd
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 5 pin assignment pin description: pins in bold have different functionality in comparison to the as3910. 9vsp_rf analog output supply regulator output for antenna drivers 10 rfo1 antenna driver output 11 rfo2 12 vsn_rf supply pad ground of antenna drivers 13 trim1_3 analog i/o input to trim antenna resonant circuit 14 trim2_3 15 trim1_2 16 trim2_2 17 trim1_1 18 trim2_1 19 trim1_0 20 trim2_0 21 v ss supply pad ground, die substrate potential 22 rfi1 analog input receiver input 23 rfi2 24 agd analog i/o analog reference voltage 25 csi analog input capacitor sensor input 26 vsn_a supply pad analog ground 27 irq digital output interrupt request output 28 mcu_clk microcontroller clock output 29 miso digital output / tristate serial peripheral interface data output 30 mosi digital input serial peripheral interface data input 31 sclk serial peripheral interface clock 32 /ss serial peripheral interface enable (active low) # vss exposed pad ground, die substract potential, connect to vss on pcb pin number pin name pin type description 32-pin qfn
AS3911B C 6 ams datasheet: 2014-jun-12 [v1-08] absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated under operating conditions on page 8 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. figure 5: absolute maximum ratings symbol parameter min max unit comments electrical parameters v dd dc supply voltage -0.5 6.0 v v dd_io dc_io supply voltage -0.5 6.0 v v intrim input pin voltage trim pins -0.5 25.0 v v in input pin voltage for peripheral communication pins -0.5 6.5 v v ina input pin voltage for analog pins -0.5 6.0 v i scr input current (latch-up immunity) -100 100 ma norm: jedec 78 i outmax drive capability of output driver 0500ma electrostatic discharge esd electrostatic discharge 2 kv standard mil-std-883-j-3015.9 (human body model) 500 v valid for trimx.x pins (pins 13 - 20) continuous power dissipation p t total power dissipation (all supplies and outputs) 300 mw absolute maximum ratings
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 7 absolute maximum ratings temperature ranges and storage conditions t strg storage temperature -55 125 c t body package body temperature 260 c norm: ipc/jedec j-std-020. the reflow peak soldering temperature (body temperature) is specified according ipc/jedec j-std-020 moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 585% moisture sensitive level 3 represents a max. floor life time of 168 h thermal resistance ja theta ja 36.4 c/w @ 85c room temperature, power consumption 1w symbol parameter min max unit comments
AS3911B C 8 ams datasheet: 2014-jun-12 [v1-08] electrical characteristics all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical quality control) methods. operating conditions all defined tolerances for external components in this specification need to be assured over the whole operation condition range and also over lifetime. figure 6: operating conditions dc/ac characteristics for digital inputs and outputs cmos inputs: valid for input pins /ss, mosi, and sclk figure 7: cmos inputs symbol parameter min max unit comments v dd positive supply voltage 2.4 5.5 v in case power supply is lower than 2.6 v, pssr cannot be improved using internal regulators (minimum regulated voltage is 2.4 v) v dd_io peripheral communication supply voltage 1.65 5.5 v v ss negative supply voltage 0 0 v t jun junction temperature -40 125 c v rfi_a rfi input amplitude 150 m 3 v pp minimum rfi input signal definition is meant for nfc receive mode. in hf reader mode and nfc transmit mode, the recommended signal level is 2.5 v pp symbol parameter min max unit v ih high level input voltage 0.7 * v dd_io v dd_io v v il low level input voltage vss 0.3 * v dd_io v i leak input leakage current -1 1 a electrical characteristics
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 9 electrical characteristics cmos outputs: valid for output pins miso, irq and mcu_clk, io_18 =0 ( see io configuration register 2 on page 67. ). figure 8: cmos outputs electrical specification v dd = 3.3 v, temperature 25c unless noted otherwise. 3.3v supply mode, regulated voltages set to 3.4 v, 27.12 mhz xtal connected to xto and xti. figure 9: electrical specification symbol parameter conditions min typ max unit v oh high level output voltage i source = 1ma i sink = 1ma 0.9 * v dd_io v dd_io v v ol low level output voltage 0 0.1 * v dd_io v c l capacitive load 0 50 pf r o output resistance 0 250 550 r pd pull-down resistance pin mosi pull-down can be enabled while miso output is in tristate. the activation is controlled by register setting. 51015k symbol parameter min typ max unit comments i pd supply current in power-down mode 0.2 0.7 2 a register 00 h set to 0f h (no clock on mcu_clk), register 01 h set to 80 h (3v supply mode), register 02 h set to 00 h register 03 h set to 08 h , other registers in default state. i nfct supply current in initial nfc target mode 2.2 3.5 7 a register 00 h set to 0f h (no clock on mcu_clk), register 01 h set to 80 h (3v supply mode), register 02 h set to 00 h register 03 h set to 80 h (enable nfc target mode), other registers in default state.
AS3911B C 10 ams datasheet: 2014-jun-12 [v1-08] electrical characteristics i wu supply current in wake-up mode 1.6 3.6 6 a register 00 h set to 0f h (no clock on mcu_clk), register 01 h set to 80 h (3v supply mode), register 02 h set to 04 h (enable wake-up mode), register 03 h set to 08 h , register 31 h set to 08 h (100ms timeout, irq at every timeout), other registers in default state. i cs capacitive sensor supply current 0.6 1.1 2 ma register 00 h set to 0f h (no clock on mcu_clk), register 01 h set to 80 h (3 v supply mode), register 02 h set to 00 h , analog test mode 14, other registers in default state. i rd supply current in ready mode 45.47.5ma register 00 h set to 0f h (no clock on mcu_clk), register 01 h set to c0 h (3 v supply mode, disable vsp_d), register 02 h set to 80 h , register 03 h set to 08 h , other registers in default state, short vsp_a and vsp_d. i al supply current all active 6.2 8.7 12.5 ma register 00 h set to 0f h , register 01 h set to c0 h (3v supply mode, disable vsp_d), register 02 h set to e8 h (one channel rx, enable tx), register 03 h set to 08, register 0b h set to 00, register 27 h set to ff (all rfo segments disabled), other registers in default state, short vsp_a and vsp_d. i lp supply current all active, low power receiver mode 4.8 6.8 10 ma register 00 h set to 0f h , register 01 h set to c0 h (3v supply mode, disable vsp_d), register 02 h set to e8 h (one channel rx, enable tx), register 03 h set to 08, register 0b h set to 80 (low power mode), register 27 h set to ff (all rfo segments disabled), other registers in default state, short vsp_a and vsp_d. symbol parameter min typ max unit comments
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 11 electrical characteristics r rfo rfo1 and rfo2 driver output resistance 0.25 0.6 1.8 i rfo = 10 ma the following measurement procedure which cancels resistance of measurement setup is used: ? all driver segments are switched on, resistance is measured, ? all driver segments except the msb segment are switched on, resistance is measured, ? difference between the two measurements is resistance of msb segment, ? resistance of msb segment multiplied by two is the value of r rfo . z load load impedance across rfo1 & rfo2 81050 using load impedance lower than minimum value can result in permanent damage of the ic v rfi rfi input sensitivity 0.5 mv rms f sub =848 khz, am channel with peak detector input stage selected. r rfi rfi input resistance 51015k v por power on reset voltage 1.5 1.65 2.0 v v agd agd voltage 1.4 1.5 1.6 v register 00 h set to 0f h (no clock on mcu_clk), register 01 h set to c0 h (3 v supply mode, disable vsp_d), register 02 h set to 80 h , register 03 h set to 08 h , other registers in default state, short vsp_a and vsp_d. v reg regulated voltage 2.85 3.0 3.15 v manual regulator mode, regulated voltage set to 3.0 v, measured on pin vsp_rf: register 00 h set to 0f h , register 01 h set to 80 h (3v supply mode), register 02 h set to e8 h (one channel rx, enable tx), register 2a h set to d8 h . t osc oscillator start-up time 0.65 0.7 10 ms 13.56mhz or 27.12mhz crystal esr max = 150 max, load capacitance according to crystal specification, irq is issued once the oscillator frequency is stable. this parameter changes with esrmax parameter. symbol parameter min typ max unit comments
AS3911B C 12 ams datasheet: 2014-jun-12 [v1-08] detailed description figure 10: minimum configuration with single side d antenna driving including emc filter figure 11: minimum configuration with differential antenna driving including emc filter detailed description antenna coil vdd /ss miso mosi sclk irq mcu_clk rf01 rf02 rfi1 rfi2 AS3911B c +2.4 v ~ +5.5 v trim1_x trim2_x cso csi agd vss vsp_a vsp_rf vsn_rf vsn_a vdd_io xti xto +1.65 v ~ +5.5 v vsp_d vsn_d
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 13 detailed description transmitter the transmitter incorporates drivers which drive external antenna through pins rfo1 and rfo2. single sided and differential driving is possi ble. the transmitter block additionally contains a sub-block which modulates transmitted signal (ook or configurable am modulation). the AS3911B transmitter is indent ed to directly drive antennas (without 50 cable, usually antenna is on the same pcb). op- eration with 50 cable is also possible, but in that case some of the advanced features are not possible. by applying ffh to the register 27h, the output driver are in tristate. receiver the receiver detects transponde r modulation superimposed on the 13.56mhz carrier signal. the receiver contains two receive chains (one for am and another for pm demodulation) which are composed of a peak detector followed by two gain and filtering stages and a final digitizer stage. the filter characteristics are adjusted to optimize performance over different iso modes and bit rates (sub-carrier frequencies from 212 khz to 6.8 mhz are supported). the receiver chain inputs are rfi1 and rfi2 pins; output of digitizer stage is demodulated sub-carrier signal. the receiver chain incorporates several features which enable reliable operation in challenging phase and noise conditions. phase and amplitude detector the phase detector is observing the phase difference between the transmitter output signals (rfo1 and rfo2) and the input signals rfi1 and rfi2. signals rfi1 and rfi2 are proportional to the signal on the antenna lc tank. rfi1 and rfi2 signals are also used to run the self-mixer whic h generates output proportional to their amplitude. the phase detector and self-mixer blocks are used for several purposes: ? pm demodulation by observing rfi1 and rfi2 phase variation (lf signal is fed to the receiver) ? average phase difference be tween rfox pins and rfix pins is used to check antenna tuning ? output of mixer is used to measure amplitude of signal present on pins rfi1 and rfi2 a/d converter the AS3911B contains a built in a/d converter. its input can be multiplexed from different sources and is used in several applications (measurement of rf amplitude and phase, calibration of modulation depth). the result of a/d conversion is stored in a register which can be read through the spi interface.
AS3911B C 14 ams datasheet: 2014-jun-12 [v1-08] detailed description capacitive sensor the capacitive sensor is used to implement low power detection of transponder presence . capacitive sensor performs measurement of capacitance between its two electrodes. presence of an object (card, hand) changes the capacitance. during calibration the reference capacitance, which represents parasitic capacitance of environment is stored. in normal operation capacitance is periodically measured and compared to stored reference value. when the measured capacitance is larger than stored reference value (threshold value can be defined in a register) an interrupt is sent to external controller. external field detector the external field detector is a low power block which is used in nfc mode to detect presence of external rf field. it supports two different detection thresholds, peer detection threshold and collision avoidance threshold. peer detection threshold is used in the nfcip-1 target mode to detect presence of initiator field. it is also used in active communication initiator mode to detect activation of target field. collision avoidance threshold is used to detect a presence of rf field during nfcip-1 rf collision avoidance procedure. quartz crystal oscillator the quartz crystal oscillator can operate with 13.56 mhz and 27.12 mhz crystals. at start-up the transconductance of the oscillator is increased to achieve fast start-up. since the start-up time varies depending on crystal type, temperature and other parameters, the oscillator amplitude is observed and an interrupt is sent when stable op eration is reached to inform the controller that the clock signal is stable and reader field can be switched on. the use of 27.12 mhz crystal is mandatory in case vhbr framing is used. it also provides a clock signal to the external microcontroller (mcu_clk) according to setting in the control register. power supply regulators integrated power supply regulators ensure high power supply rejection of a complete reader sy stem. in case psrr of the reader system has to be im proved, the command adjust regulators is sent. as result of this command, the power supply level of v dd is measured in maximum load conditions and the regulated voltage reference is set 250 mv below this measured level to assure a stable regulated supply. the resulting regulated voltage is stored in a register. it is also possible to define regulated voltage by writing a configuration register. in order to decouple any noise sources from different parts of ic there are three regulators integrated with separated external blocking capacitors (regulated voltage of all is the same in 3.3 v supply mode). one regulator is for the analog blocks, one for
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 15 detailed description digital blocks, there is also a separate one for the antenna drivers. in case of low cost applications some (or all) regulators may not be used to save on external components. this block additionally generates a reference voltage for the analog processing (agd - analog ground). this voltage also has an associated external buffer capacitor. por and bias this block contains the bias current and voltage generator which provides bias currents and reference voltages to all other blocks. it also incorporates a power on reset (por) circuit which provides a reset at power-up and at low supply levels. rc oscillator and wake-up timer the AS3911B includes several possibilities of low power detection of a card presence (capacitive sensor, phase measurement, amplitude measurement). rc oscillator and register configurable wake-up timer are used to schedule periodic detection. when presence of a card is detected an interrupt is sent to controller. iso14443 and nfcip-1 framing this block performs framing for receive and transmit according to the selected iso mode and bit rate settings. in reception it takes demodulated sub-carrier signal from receiver. it recognizes the sof, eof and data bits, performs parity and crc check, organizes the received data in bytes and places them in the fifo. during transmit, it operates inversely, it takes bytes from fifo, generates parity and crc bits, adds sof and eof and performs final encoding before passing modu lation signal to transmitter. in transparent mode, the framing and fifo are bypassed, the digitized sub-carrier signal, which is receiver output, is directly sent to miso pin, signal applied to mosi pin is directly used to modulate the transmitter. fifo the AS3911B contains a 96 byte fifo. depending on the mode, it contains either data which has been received or data which is to be transmitted. control logic the control logic contains i/o registers which define operation of device.
AS3911B C 16 ams datasheet: 2014-jun-12 [v1-08] application information spi interface a 4-wire serial peripheral interface (spi) is used for communication between external microcontroller and the AS3911B. operating modes the AS3911B operating mode is de fined by the contents of the operation control register . at power-up all bits of the operation control register are set to 0, the AS3911B is in power-down mode. in this mode afe static power consumption is minimized, only the por and part of the bias are active, the regulators are transparent and are not operating. the spi is still function al in this mode so all settings of iso mode definition and configuration registers can be done. control bit en (bit 7 of the operation control register ) is controlling the quartz crystal oscillator and regulators. when this bit is set, the device enters in ready mode. in this mode the quartz crystal oscillator and regulators are enabled. an interrupt is sent to inform the microcontroller when the oscillator frequency is stable. enable of receiver and transm itter are separated so it is possible to operate one without switching on the other (control bits rx_en and tx_en ). in some cases this may be useful, in case the reader field has to be maintained and there is no transponder response expected rece iver can be switched-off to save current. another example is nfcip-1 active communication receive mode in wh ich rf field is generated by the initiator and only receiver operates. asserting the operation control register bit wu while the other bits are set to 0 puts the AS3911B into the wake-up mode which is used to perform low power detection of card presence. in this mode the low power rc oscillator and register configurable wake-up timer are used to schedule periodic measurement(s). when a difference to the predefined reference is dete c ted an inte r r up t is sent to wake -u p the m icro. ca pa citive sensor, phase measurement and amplitude measurement are available. transmitter the transmitter contains two identical push-pull driver blocks connected to the pins rfo1 and rfo2. these drivers are differentially driving external ante nna lc tank. it is also possible to operate only one of the two drivers by setting the io configuration register 1 bit single. each driver is composed of 8 segments having binary weighted output resistance. the msb segment typical on resistance is 2 , when all segments are turned on; the output resistance is typically 1 . usually all segments are turned on to de fine the normal transmission application information
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 17 application information (non-modulated) level. it is also possible to switch off certain segments when driving the non-modulated level to reduce the amplitude of signal on the antenna and/or to reduce the antenna q factor without making any hardware changes. the rfo normal level definition register defines which segments are turned on to define the normal transmission (non-modulated) level. default se tting is that all segments are turned on. using the single driver mode the number and therefore the cost of the antenna lc tank components is halved, but also the output power is reduced. in single mode it possible to connect two antenna lc tanks to the two rfo outputs and multiplex between them by controlling the io configuration register 1 bit rfo2 . in order to transmit the data th e transmitter output level needs to be modulated. the am and ook modulation are supported. the type of modulation is defined by setting the bit tr_am in the auxiliary definition register . for the operation modes supported by the AS3911B framing the setting of modulation type is done automatically by sending direct command analog preset . during the ook modulation (for example iso14443a) the transmitter drivers stop driving the carrier frequency; drivers are frozen in state before the modulation. as consequence the amplitude of the antenna lc tank oscillation decays, the time constant of the decay is defined with the lc tank q factor. the decay time in case of ook modulation can be shortened by asserting the auxiliary definition register bit ook_hr . when this bit is set to logic one the driver s are put in tristate during the ook modulation. am modulation (for example iso14443b) is done by increasing the output driver impedance during the modulation time. this is done by reducing the number of driver segments which are turned on. the am modulated level can be automatically adjusted to the target modulation depth by defining the target modulation depth in the am modulation depth control register and sending the calibrate modulation depth direct command. please refer to am modulation depth: definition and calibration for further details.
AS3911B C 18 ams datasheet: 2014-jun-12 [v1-08] application information slow transmitter ramping when transmitter is enabled it starts to drive the antenna lc tank with full power, the ramp ing of field emitted by antenna is defined by antenna lc tank q factor. however there are some reader systems where the reader field has to transition with a longer transition time when it is enabled. the stif (syndicat des transports d'ile de france) specification requires a transition time from 10% to 90% of field longer than or equal to 10 s. the AS3911B supports that feature. it is realized by collapsing vsp_rf regulated voltage when transmitter is disabled and ramping it when transmitter is en abled. typical transition time is 15 s at 3 v supply and 20 s at 5 v supply. procedure to implement the slow transition: ? when transmitter is disabled set io configuration register 2 bit slow_up to 1. keep this state at least 2 ms to allow discharge of vsp_rf. ? enable transmitter, its output will ramp slowly. ? before sending any command set the bit slow_up back to 0. receiver the receiver performs demodulation of the transponder sub-carrier modulation which is superimposed on the 13.56mhz carrier frequency. it performs am and/or pm demodulation, amplification, band-pass filtering and digitalization of sub-carrier signals. additionally it performs rssi measurement, automatic gain control (agc) and squelch function. in typical application the receiv er inputs rfi1 and rfi2 are outputs of capacitor dividers connected directly to the terminals of antenna coil. such concept assures that the two input signals are in phase to the voltage on antenna coil. care has to be taken during design of capacitive divider that the rfi1 and rfi2 input signal pp value does not exceed the vsp_a supply voltage. receiver comprises two complete receive channels for am demodulation and pm demodulation. in case both channels are active the selection of channel used for reception framing is done automatically by receive framing logic. the receiver is switched on when operation control register bit rx_en is set to one. additionally the operation control register contains bits rx_chn and rx_man ; rx_chn defines whether both, am and pm, demodulation channels will be active or only one of them, while bit rx_man defines the channel select ion mode in case both channels are active (automatic or manual). operation of the receiver is controlled by four receiver configuration registers. the operation of the receiver is additionally controlled by the signal rx_on which is set high when modulated signal is expected on the receiver input. this signal is used to control
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 19 application information rssi and agc and also enables processing of receiver output by framing logic. signal rx_on is automatically set high after mask receive timer expires. signal rx_on can also be directly controlled by the controller by sending direct commands mask receive data and unmask receive data . figure 12 illustrates the receiver block diagram. demodulation stage first stage performs demodulation of transponder sub-carrier response signal, which is superimposed on hf field carrier. two different blocks are implemented for am demodulation: peak detector and am demodulator mixer. the choice of the demodulator, which is used, is made by the receiver configuration register 1 bit amd_sel . peak detector performs am demo dulation using peak follower. both, the positive and negative peaks are tracked to suppress common mode signal. it is limited in speed; it can operate for sub-carrier frequencies up to fc/8 (1700 khz). it has demodulation gain g = 0.7. it s input is taken from one demodulator input only (usually rfi1). am demodulator mixer uses synchronous rectification of both receiver inputs (rfi1 and rfi2). its gain is g = 0.55. mixer demodulator is optimized for vh br sub-carrier frequencies. (fc/8 and higher). for sub-carrier frequency fc/8 (1700 khz) both peak follower and mixer can be used, while for fc/4 and fc/2 are supported only by mixer. by default the peak detector is used, for data rates fc/8 and higher use of mixer is automatically preset by sending direct command analog preset . pm demodulation is also done by a mixer. the pm demodulator mixer has differential outputs with 60mv differential signal for 1% phase change (16.67 mv per degree). its operation is optimized for sub-carrier freque ncies up to fc/8 (1700 khz). in case the demodulation is done externally of the AS3911B it is possible to multiplex the lf signals applied to pins rfi1 and rfi2 directly to the gain and filtering stage by selecting the receiver configuration register 2 bit lf_en .
AS3911B C 20 ams datasheet: 2014-jun-12 [v1-08] application information figure 12: receiver block diagram filtering and gain stages the receiver chain has band pa ss filtering characteristics. filtering is optimized to pass sub-carrier frequencies while rejecting carrier frequency and low frequency noise and dc component. filtering and gain is implemented in three stages where the first and the last stage have the first order high pass characteristics, while the mid stage has second order low pass characteristic. gain and filtering characteristics can be optimized for current application by writing the receiver configuration register 1 (filtering), receiver configuration register 3 (gain in first stage) and receiver configuration register 4 (gain in second and third stage). gain of first stage is about 20db and can be reduced in six 2.5 db steps. there is also a special boost mode available, which boosts the maximum gain for additi onal 5.5 db. in case of vhbr (fc/8 and fc/4) the gain is lower. the first stage gain can only be modified by writing receiver configuration register 3 . the default setting of this register is the minimum gain. default first stage zero is located at 60 khz, it can also be lowered to 40khz or 12 khz by writing option bits in the receiver configuration register 1 . the control of the first and third stage zeros is done with common control bits (see figure 14 ). digital sub-carrier am demodulator mixer peak detector agc squelch rssi rec4<7:4> agc squelch rssi rec4<3:0> rec3<7:5> rec3<4:2> rec3<2:0> rec1<5:3> digital sub-carrier ac coupling + 1 st gain stage low-pass + 2 nd gain stage high-pass + 3 rd gain stage digitizing stage demodulation stage m u x pm demodulator mixer rec1<7:6> rec2<6:5> rf_in1 rf_in2 rssi_am<3:0> rssi_pm<3:0> rx_on sg_on
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 21 application information gain in the second and third stag e is 23 db and can be reduced in six 3 db steps. gain of thes e two stages is included in agc and squelch loops or can be manually set in receiver configuration register 4 . sending of direct command reset rx gain is necessary to initialize th e agc, squelch and rssi block. sending this command clears the current squelch setting and loads the manual gain reduction from receiver configuration register 4 . second stage has a second order low pass filtering characteristic, the pass band is adjusted according to sub-carrier frequency using th e bits lp2 to lp0 of the receiver configuration register 1 . see figure 13 for -1db cut-off frequency for different settings. figure 13: low pass control figure 14: first and third stage zero setting rec1<5> lp2 rec1<4> lp1 rec1<3> lp0 -1 db point 0 0 0 1200 khz 001600 khz 010300 khz 1002 mhz 101 7 mhz other not used rec1<2> h200 rec1<1> h80 rec1<0> z12k first stage zero third stage zero 0 0 0 60 khz 400 khz 1 0 0 60 khz 200 khz 01040 khz80 khz 0 0 1 12 khz 200 khz 01112 khz80 khz 1 0 1 12 khz 200 khz other not used
AS3911B C 22 ams datasheet: 2014-jun-12 [v1-08] application information figure 15 provides information on the recommended filter settings. for all supported operation modes and receive bit rates there is an automatic preset defined, additionally some alternatives are listed. automatic preset is done by sending direct command analog preset . there is no automatic preset for steam and transparent modes. since selection of filter characteristics also modifies ga in, the gain range for different filter settings is also listed. figure 15: receiver filter selection and gain range digitizing stage digitizing stage is producing a di gital form of sub-carrier signal which is output of receiver and input to framing logic. it is a window comparator with adjust able digitizing window (five possible settings, 3 db steps, adjustment range from 33 mv to 120 mv). adjustment of the digitizing window is included in agc and squelch loops or can be manually set in receiver configuration register 4 . rec1<5:3> lp<2:0> rec1<2> h200 rec1<1> h80 rec1<0> z12k gain [db] comment max all min1 max23 max1 min23 min all with boost 000 0 0 0 43.4 28 26.4 11 49.8 automatic preset for iso14443a fc/128 and nfc forum type 1 tag 000 1 0 0 44 29 27.5 12 49.7 automatic preset for iso14443b fc/128 iso14443 fc/64 001 1 0 0 44.3 29 27 11.7 49.8 recommended for 424/484 khz sub-carrier 000 0 1 0 41.1 25.8 23.6 8.3 46.8 alternative choice for iso14443 fc/32 and fc/16 100 0 1 0 32 17 17.2 2 37.6 automatic preset for iso14443 fc/32 and fc/16 alternative choice for fc/8 (1.7 kb/s) 100 0 0 0 32 17 17.2 2 37.6 alternative choice for fc/8 (1.7 kb/s) 000 0 1 1 41.1 25.8 23.6 8.3 46.8 automatic preset felica (fc/64, fc/32) alternative choice for iso14443 fc/32 and fc/16 101 0 1 0 30 20 12 2 34 alternative choice for fc/8 and fc/4 101 1 0 0 30 20 12 2 34 automatic preset for fc/8 and fc/4 000 1 0 1 36.5 21.5 24.9 9.9 41.5 automatic preset for nfcip-1 (initiator and target)
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 23 application information agc, squelch and rssi as mentioned above second and third gain stage gain and the digitizing stage digitizing window are included in agc and squelch loops. eleven settings are available, default state features minimum digitizer window and maximum gain, first four steps increase the digitizer window in 3 db steps, next six steps additionally reduce the gain in 2 nd and 3 rd gain stage also in 3 db steps. the initial setti ng with which squelch and agc start is defined in receiver configuration register 4 . the gain reduction state register displays the actual state of gain which results from squelch, ag c and initial settings in receiver configuration register 4 . during bit anticollision like type a, the agc should be disabled. squelch this feature is designed for op eration of receiver in noisy environment. the noise can come from tags in which processing of data sent by the reader is going on and an answer is being prepared. noise can also be generated by noisy environment. this noise may be misinterpreted as start of transponder response which re sults in decoding error. during execution of the sque lch procedure the output of digitizing comparator is observed. in case there are more than two transitions on this output in 50 s time period, gain is reduced for 3 db and output is observed during next 50 s. this procedure is repeated until number of transitions in 50 s is lower or equal to 2 or until maximum gain reduction is reached. this setting is cleared by sending direct command reset rx gain . there are two possibilities of performing squelch: automatic mode and using direct command squelch . ? automatic mode is started in case bit sqm_dyn in the receiver configuration register 2 is set. it is activated automatically 18.88 s after en d of tx and is terminated with mask receive timer expi re. this mode is primarily intended to suppress noise ge nerated by tag processing during the time when the ta g response is not expected (covered by mask receive timer). ? command squelch is accepted in case it is sent when signal rx_on is low. it can be used in case the time window in which noise is present is known by the controller. agc agc (automatic gain control) is used to reduce gain to keep receiver chain out of saturation. in case gain is properly adjusted the demodulation proce ss is also less influenced by system noise. agc action starts when signal rx_on is asserted high and is reset when it is reset to low. at low to high transitions of the rx_on the state of the receiver gain is stored in the gain reduction state register , therefore reading this register later gives the information of the gain setting used during last reception.
AS3911B C 24 ams datasheet: 2014-jun-12 [v1-08] application information when agc is switched on receiver gain is reduced so that the input to digitizer stage is not saturated. the agc system comprises a window comparator which has its window 3.5 times larger than window of digitalization window comparator. when the agc function is enabled gain is reduced until there are no transitions on its output. such procedure assures that the input to digitalization window comparator is less than 3.5 times larger than its window. agc operation is controlled by the control bits agc_en , agc_m and agc_fast in the receiver configuration register 2 . bit agc_en enables the agc operation; bit agc_m defines the agc mode while bit agc_alg define the agc algorithm. two agc modes are available, agc can operate during complete rx process (as long as signal rx_on is high) or it can be enabled only during first eight sub-carrier pulses. two agc algorithms are available; agc can either start by presetting of code 4 h (max digitizer window, max gain) or by resetting the code to 0 h (min digitizer window, max gain). algorithm with preset code is faster, therefore it is recommended for protocols with short sof (like iso14443a fc/128). default agc settings are: agc is enabled, agc operates during complete rx process, algorithm with preset is used. rssi the receiver also performs the rssi (received signal strength indicator) measurement of both channels. rssi measurement is started after rising edge of rx_on . it stays active while signal rx_on is high; while rx_on is low it is frozen. it is a peak hold system; the value can only increase from initial zero value. every time the agc reduces the gain the rssi measurement is reset and starts from zero. result of rssi measurements is 4-bit value which can be observed by reading the rssi display register . the lsb step is 2.8 db, the maximum code is d h (13 d ). since the rssi measurement is of peak hold type the rssi measurement result does not follow any variations in the signal strength (the highest value will be kept). in order to follow rssi variation it is possible to reset rssi bits and restart the measurement by sending direct command clear rssi . receiver in nfcip-1 active communication mode there are several features built in receiver to enable reliable reception of active nfcip-1 communication. all these settings are automatically preset by sending direct command analog preset after the nfcip-1 mode has been configured. in addition to filtering options there are two nfc specific configuration bits stored in the receiver configuration register 3 . bit lim enables clipping circuits which are positioned after first and second gain stages. the intention of clipping circuits is to limit the signal level for the following filtering stage (in case the nfc peer is close the input signal level can be quite high).
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 25 application information bit rg_nfc forces gain reduction of second and third filtering stage to -6db while keeping the digitizer comparator window at maximum level. capacitive sensor the capacitive sensor block pro vides a possibility of low power detection of tag presence. the capacitive measurement system comprises two electrodes. one is excitation electrode emitting electrical field of a fixed frequency in range of few hundred khz (cso) and the second one is the sensing electrode (csi). the amount of charge gen- erated in sensing electrode represents the capacitance be- tween the two electrodes. capacitive sensor electrodes are tol- erant to parasitic capacitance to ground (up to 25 pf) and to input leakage (up to 1 m ). since the charge on the sensing electrode is generated with the frequency of excitation electrode, synchronous rectifier is used to detect it. this ensures good rejection of interference and high tolerance to parasitic capacitances (to all nodes except the excitation electrode). capacitive sensor system depict ed on figure below uses a syn- chronous rectifier to convert the ac charge generated by the excitation signal on the sensing electrode. this yields a dc out- put voltage, which is linearly proportional to the capacitance between the excitation and sensing electrode. the output dc voltage is converted by an ad converter in absolute mode. re- sult is stored in the a/d converter output register (see also a/d converter ). figure 16: capacitive sensor block diagram a/d converter synchronous rectifier oscillator cso csi
AS3911B C 26 ams datasheet: 2014-jun-12 [v1-08] application information any conductive object (human hand or tag's antenna windings) approaching the two electrodes changes the capacitance between the excitation and sensing electrode as it 'shortens' the distance between the two by providing conductance on the part of the path between the two electrodes. capacitance measurement is started by sending direct command measure capacitance . the AS3911B can also be configured to periodically wake-up and perform the capacitance measurement. the result is compared to a stored reference or to an average of previous measurements and in case the difference is greater than a predefined value an irq is triggered to wake-up the controller (see also wake-up mode ). capacitor sensor gain can be adjusted by setting in capacitive sensor control register . default gain is 2.8 v/pf typ., maximum gain is 6.5 v/pf typ. since lsb of ad converter corresponds to approximately 7.8mv, the default gain results in sensitivity of 2.8 ff/lsb (1.2 ff/lsb maximum). capacitance measurement duration is 200 s, current consumption during measurement is 1.1 ma typ. in case capacitive measurement is performed every 100 ms in wake-up mode the resulting typical average consumption is 5.8 a (3.6 a is standby consumption in wake-up mode). capacitor sensor calibration capacitor sensor comprises ca libration unit internally compensates the parasitic capacitances between csi and cso, thus leaving full measurement range for information about capacitance variation. 5 bits are used to control the calibration, minimum calibration step is 0.1pf, calibration range is 3.1 pf. calibration can be done manually by writing capacitive sensor control register or automatically by sending direct command calibrate capacitive sensor . the status of calibrate capacitive sensor command and resulting calibration value are stored in the capacitive sensor display register . in order to avoid interference of capacitive sensor with xtal oscillator and reader magnetic field and to assure repetitive results it is strongly recomme nded to perform capacitance measurement and calibration in power-down mode only.
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 27 application information wake-up mode asserting the operation control register bit wu while the other bits are set to 0 puts the AS3911B into the wake-up mode which is used to perform low power detection of card presence. the AS3911B includes several possibilities of low power detection of a card presence (capacitive sensor, phase measurement, amplitude measurement). low power 32 khz rc oscillator and register configurable wake-up timer are used to schedule periodic detection. usually the presence of a card is detected by so called polling. in this process the reader is periodically turned on and the controller activates the protocol to check whether a card is present. such procedure consumes a lot of energy since reader field has to be turned on for 5 ms before a command can be issued. low power detection of card presence is performed by detecting a change in reader environment, which is produced by presence of a card. when a change is detected, an interrupt is sent to the controller. as a result, the controller can activate the protocol for tag detection. in the wake-up mode the AS3911B periodically performs the configured measurements and sends an irq to the controller, which is in deep sleep to mini mize the current consumption, only when a difference to the build in reference is detected. detection of card presence can be done by performing phase, amplitude and capacitive sensor measurements. presence of a card close to the reader antenna coil produces due to the magnetic coupling of the two coils a change of the antenna lc tank signal phase and amplitude. the reader field activation time needed to perform the phase or the amplitude measurement is extremely shor t (~20 s) comparing to the activation time needed to send a protocol activation command. additionally the power level during the measurement can be lower than the power level during normal operation since the card does not have to be powered to produce the coupling effect. the emitted power can be reduced by increasing the rfo normal level definition register . capacitance sensor detects a change of the parasite capacitance between the two excitation electrodes which is caused by a card antenna and a hand holding it. see capacitive sensor on page 14 for a detailed information on the capacitive sensor. the registries on locations from 31 h to 3d h are dedicated to wake-up configuration and display. the wake-up timer control register is the main wake-up mode configuration register. the timeout period between the su ccessive detections and the measurements which are going to be used are selected in this register. timeouts in the range from 10 ms to 800 ms are
AS3911B C 28 ams datasheet: 2014-jun-12 [v1-08] application information available, 100 ms is the default value. any combination of available measurements can be selected (one, two or all of them). the following twelve registers (32 h to 3d h ) are configuring the three possible detection measurements and storing the results, four registers are used for each measurement. an irq is sent when the difference between a measured value and reference value is larger than configured threshold value. there are two possibilities how to define the reference value: ? the AS3911B can calculate the reference based on previous measurements (auto-averaging) ? the controller determines the reference and stores it in a register the first register in the series of four is the measurement configuration register (see for e.g. amplitude measurement configuration register ). the difference to reference which triggers the irq, the method of reference value definition and the weight of last measurement result in case of auto-averaging are defined in this register. th e next register is storing the reference value in case the reference is defined by the controller. the following two registers are display registers. the first one stores the auto-averaging reference; the second one stores the result of the last measurement. wake-up mode configuration registers have to be configured before wake-up mode is actually entered. any modification of wake-up mode configuration while it is active may result in unpredictable behavior. auto-averaging in case of auto-averaging the reference value is recalculated after every measurement. the last measurement value, the old reference value and the weight are used in this calculation. the following formula is used to calculate the new reference value. the calculation is done on 10 bits to have sufficient precision. the auto-averaging process is initialized when wake-up mode is first time entered after initialization (power-up or using set default command). the initial value is taken from the measurement display register (for example amplitude measurement display register ) until the content of this register is not zero. every measurement configuration register contains a bit which defines whether the measurement which causes an interrupt is taken in account for the average value calculation (for example bit am_aam of the amplitude measurement configuration reg- ister ). newaverage oldaverage oldaverage measuredvalue ? weight -------------------------------------------------------------------------------- + =
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 29 application information quartz crystal oscillator the quartz crystal oscillator can operate with 13.56 mhz and 27.12 mhz crystals. the operation of quartz crystal oscillator is enabled when the operation control register bit en is set to one. an interrupt is sent to inform the microcontroller when the oscillator frequency is stable (see main interrupt register ). the status of oscillator can be observed by observing the auxiliary display register bit osc_ok . this bit is set to 1 when oscillator frequency is stable. the oscillator is based on an inverter stage supplied by controlled current source. a feedback loop is controlling the bias current in order to regulate amplitude on xti pin to 1 v pp . this feedback assures reliable operation even in case of low quality crystals with r s u p t o 5 0 . in order to enable a fast reader start-up an interrupt is sent when oscillator amplitude exceeds 750 mv pp . division by two assures that 13.56 mhz signal has a duty cycle of 50% which is better for the transmitter performance (no pw distortion). use of 27.12 mhz crystal is therefore recommended for better performance. in case of 13.56 mhz crystal, th e bias current of stage which is digitizing oscillator signal is increased to assure as low pw distortion as possible. please note that in case of vhbr reception (bit rates fc/8 and above) it is mandatory to use the 27.12 mhz crystal since high frequency clock is need ed for receive framing. the oscillator output is also used to drive a clock signal output pin mcu_clk), which can be used by the external microcontroller. the mcu_clk pin is configured in the io configuration register 2 . timers the AS3911B contains several timers which eliminate the need to run counters in the controller, thus reducing the effort of the controller code implementation and improve portability of code to different controllers. every timer has one or more asso ciated configuration registers in which the timeout duration and different operating modes are defined. these configuration registers have to be set while the corresponding time r is not running. any modification of timer configuration while the timer is active may result in unpredictable behavior. all timers except the wake-up timer are stopped by direct command clear . exception : in case bit nrt_emv in the general purpose and no-response timer control register is set to one, the no-response timer is not stopped.
AS3911B C 30 ams datasheet: 2014-jun-12 [v1-08] application information mask receive timer and no-response timer mask receive timer and no-response timer are both automatically started at the end of transmission (at the end of eof). mask receive timer the mask receive timer is blocking the receiver and reception process in framing lo gic by keeping the rx_on signal low after the end of tx during the time the tag reply is not expected. while the mask receive timer is running, the squelch is automatically turned on (if enabled). mask receive timer does not produce an irq. the mask receive timer time out is configured in the mask receive timer register . in the nfcip-1 active communication mode the mask receive timer is started when the peer nfc device (a device with which communication is going on) switches on its field. the mask receive timer has a special use in the low power initial nfc target mode. after the initiator field has been detected the controller turns on the oscillator, regulator and receiver. mask receive timer is started by sending direct command start mask-receive timer . after the mask receive timer expires the receiver output starts to be observed to detect start of the initiator message. in this mode the mask receive timer clock is additionally divided by eight it (one count is 512/fc) to cover range up to ~9.6 ms. no-response timer as its name indicates this timer is intended to observe whether a tag response was detected in a configured time started by end of transmission. the i_nre flag in the timer and nfc interrupt register is signaling interrupt events resulting from this timer timeout. the no-response timer is configured by writing two no-response timer setting registers: no-response timer register 1 and no-response timer register 2 . operation options of the no-response timer ar e defined by setting bits nrt_emv and nrt_step in the general purpose and no-response timer control register . bit nrt_step configures the time step of the no-response timer. two steps are available, 64/fc (4.72 s), which covers range up to 309 ms and 4096/fc, which covers range up to 19.8 s. bit nrt_emv controls the timer operation mode: ? when this bit is set to 0 (default mode) the irq is produced in case the no-response timer expires before a start of a tag reply is detected. in the opposite case, when start of a tag reply is detected before timeout, the timer is stopped, and no irq is produced. ? when this bit is set to 1 the timer unconditionally produces an irq when it expire s, it is also not stopped by direct command clear . this means that irq is independent of the fact whether or not a tag reply was detected. in case
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 31 application information at the moment of timeout a tag reply is being processed no other action is taken, in the opposite case, when no tag response is being processe d additionally the signal rx_on is forced to low to stop receive process. the no-response timer can also be started using direct command start no-response timer . the intention of this command is to extend the no-response timer timeout beyond the range defined in the no-response timer control registers. in case this command is sent while the timer is running, it is reset and restarted. in the nfcip-1 active communication mode the no-response timer is automatically started when the transmitter is turned off after the message has been se nt. in case this timer expires before the peer nfc device (a device with which communication is going on) switches on its field an interrupt is sent. in all modes, where timer is set to nonzero value, it is a must that m_txe is not set and interrupt i_txe is read via spi for synchronization between transmitter and timer. general purpose timer the triggering of the general purpose timer is configured by setting the general purpose and no-response timer control register . it can be used to survey the duration of reception process (triggering by start of re ception, after sof) or to time out the pcd to picc response time (triggered by end of reception, after eof). in the nfcip-1 active communication mode it is used to timeout the fi eld switching off. in all cases an irq is sent when it expires. the general purpose timer can al so be started by sending the direct command start general purpose timer . in case this command is sent while the timer is running, it is reset and restarted. wake-up timer wake timer is primarily used in the wake-up mode (see 27). additionally it can be used by sending a direct command start wake-up timer . this command is accepted in any operation mode except wake-up mode. when this command is send the rc oscillator, which is used as clock source for wake-up timer is started, timeout is defined by setting in the wake-up timer control register . when the timer expires, an irq with the i_wt flag in the error and wake-up interrupt register is sent. wake-up timer is useful in th e low power operation mode, in which other timers cannot be used (in the low power operation mode the crystal oscillator, which is clock source for the other timers, is not running). please note that the tolerance of wake-up timer timeout is defined by tolerance of the rc oscillator.
AS3911B C 32 ams datasheet: 2014-jun-12 [v1-08] application information a/d converter the AS3911B contains an 8-bit successive approximation a/d converter. input to a/d converter can be multiplexed from different sources to be used in several direct commands and adjustment procedures. the result of last a/d conversion is stored in the a/d converter output register . typical conversion time is 224/fc (16.5 s). the a/d converter has two operating modes, absolute and relative. ? in absolute mode the low reference is 0v and the high reference is 2 v. this means that a/d converter input range is from 0 to 2 v, 00 h code means input is 0 v or lower, ff h means that input is 2 v - 1lsb or higher, lsb is 7.8125 mv. ? in relative mode low reference is 1/6 of vsp_a and high reference is 5/6 of vsp_a, so the input range is from 1/6 vsp_a to 5/6 vsp_a. relative mode is only used in phase measurement (phase detector output is proportional to power supply). in all other cases absolute mode is used. phase and amplitude detector this block is used to provide input to a/d converter to perform measurements of amplitude and phase, expected by direct commands measure amplitude and measure phase . several phase and amplitude measurements are also performed by direct commands calibrate modulation depth and calibrate antenna . phase detector the phase detector is observing phase difference between the transmitter output signals (rfo 1 and rfo2) and the receiver input signals rfi1 and rfi2, which are proportional to the signal on the antenna lc tank. these signals are first passed by digitizing comparators. digitized signals are processed by a phase detector with a strong lo w pass filter characteristics to get average phase difference. the phase detector output is inversely proportional to the phase difference between the two inputs. the 90 phase shift results in vsp_a/2 output voltage, in case both inputs are in phase output voltage is vsp_a in case they are in opposite phase output voltage is zero. during execution of direct command measure phase this output is multiplexed to a/d converter input (a/d converter is in relative mode during execution of command measure phase ). since the a/d converter range is from 1/6 vsp_a to 5/6 vsp_a the actual phase detector range is from 30o to 150o. figures below depict the two inputs and output of phas e detector in case of 90o and 135o phase shift.
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 33 application information figure 17: phase detector inputs and output in case of 90o phase shift figure 18: phase detector inputs and output in case of 135o phase shift amplitude detector signals from pins rfi1 and rfi2 are used as inputs to the self-mixing stage. output of this stage is dc voltage proportional to amplitude of signal on pins rfi1 and rfi2. during execution of direct command measure amplitude this output is multiplexed to a/d converter input. vsp vsp vsp 0 vsp/2 vsp vsp 0 vsp/2 vsp
AS3911B C 34 ams datasheet: 2014-jun-12 [v1-08] application information external field detector the external field detector is used to detect the presence of an external device generating an rf field. it is automatically switched on in nfcip-1 active communication modes; it can also be used in other modes. the external field detector supports two different detectio n thresholds, peer detection threshold and collision avoidance threshold. the two thresholds can be independ ently set by writing the external field detector threshold register . the actual state of the external field detector output can be checked by reading the auxiliary display register . input to this block is the signal from the rfi1 pin. peer detection threshold this threshold is used to detect the field emitted by peer nfc device with which nfc communic ation is going on (initiator field in case the AS3911B is a target and the opposite, target field in case the AS3911B is an in itiator). it can be selected in the range from 75 mv pp to 800 mv pp . when this threshold is enabled the external field detector is in low power mode. an interrupt is generated when an external field is detected and also when it is switched off. with such implementation it can also be used to detect the moment when the external field disappears. this is useful to detect the moment when the peer nfc device (it can be either an initiator or a target) has stopped emitting an rf field. the external field detector is automatically enabled in the low power peer detection mode when nfcip-1 mode (initiator or target) is selected in the bit rate definition register . additionally it can be enabled by setting bit en_fd in the auxiliary definition register . collision avoidance threshold this threshold is used during the rf collision avoidance sequence which is executed by sending nfc field on commands (see nfc field on commands on page 53 ). it can be selected in the range from 25 mv pp to 800 mv pp .
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 35 application information power supply system the AS3911B features two positive supply pins, v dd and v dd_io . v dd is the main power supply pin. it supplies the AS3911B blocks through three regulators (v dd_a , v dd_d and v dd_rf ). v dd range from 2.4 to 5.5 v is supported. v dd_io is used to define supply level for digital communication pins (/ss, miso, mosi, sclk, irq, mcu_clk). digital communication pins interface to the AS3911B logic through level shifters, therefore the internal supply voltage can be either higher or lower than v dd_io . v dd_io range from 1.65 v to 5.5 v is supported. figure 20 shows the building blocks of the AS3911B power supply system. it contains three regulators, a power-down support block, a block generating analog reference voltage (agd) and a block performing automatic power supply adjustment procedure. the three regulators are providing supply to analog blocks (vsp_a), logic (vsp_d) and transmitter (vsp_rf). the use of vsp_a and vsp_d regulators is mandatory at 5v power supply to provide regulated voltage to analog and logic blocks which only use 3.3 v devices. the use of vsp_a and vsp_d regulators at 3 v supply and vsp_rf regulator at any supply voltage is recommended to improve system psrr. regulated voltage can be adju sted automatically to have maximum possible regulated voltage while still having good psrr. all regulator pins also have corresponding negative supply pins which are externally connected to ground potential (vss). the reason for separation is in decoupling of noise induced by voltage drops on the internal power supply lines. figure 10 and figure 11 depict typical AS3911B application schematics with all regulators used. all regulator pins and agd voltage are buffered with capacitor. recommended blocking capacitor values can be found in the table below are 2.2 f in parallel with 10 nf, for pin agd 1 f in parallel with 10 nf is suggested. figure 19: recommended blocking capacitor values pins recommended capacitors agd-vss 1f || 10nf vsp_a-vsn_a vsp_d-vsn_d 2.2f || 10nf 2.2f || 10nf vsp_rf-vsn_rf 2.2f || 10nf
AS3911B C 36 ams datasheet: 2014-jun-12 [v1-08] application information figure 20: the AS3911B power supply system regulators have two basic operation modes depending on supply voltage, 3.3 v supply mode (max 3.6 v) and 5 v supply mode (max 5.5v). the supply mode is set by writing bit sup3 v in the io configuration register 2 . default setting is 5 v so this bit has to be set to one after power-up in case of 3.3 v supply. in 3.3 v mode all regulators are set to the same regulated voltage in range from 2.4 v to 3.4 v, while in 5 v only the vsp_rf can be set in range from 3.9 v to 5.1 v, while vsp_a and vsp_d are fixed to 3.4 v. figure 20 depicts signals controlling the power supply system. the regulators are operating when signal en is high ( en is configuration bit in operation control register . when signal en is low the AS3911B is in low power power-down mode. in this mode consumption of the power supply system is also minimized. power-down support sup3v 50 ohm rv<3:0> vsp_rf reg en bgr & agc autoreg vsp_a vsp_rf 1k ohm vsp_d agd reg2bh vdd reg2ah vsp_a reg vsp_d reg adjust
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 37 application information vsp_rf regulator the intention of this regulator is to improve psrr of the transmitter (the noise of the transmitter power supply is emitted and fed back to the receiver). the vsp_rf regulator operation is controlled and obse rved by writing and reading two regulator registers: ? regulator voltage control register controls the regulator mode and regulated voltage. bit reg_s controls regulator mode. in case it is set to 0 (default state) the regulated voltage is set using direct command adjust regulators . when bit reg_s is asserted to 1 regulated voltage is defined by bits rege_3 to rege_1 of the same register. the regulated voltage adjustment range depends on the power supply mode. in case of 5 v supply mo de the adjustment range is between 3.9 v and 5.1 v in steps of 120 mv, in case of 3.3 v supply mode the adjustment range is from 2.4 v to 3.4 v with steps of 100 mv. default regulated voltage is the maximum one (5.1 v and 3.4 v in case of 5 v and 3.3 v supply mode respectively). ? regulator and timer display register i s a r e a d o n l y r e g i s t e r which displays actual regulated voltage when regulator is operating. it is especially usef ul in case of automatic mode, since the actual regulated voltage, which is result of direct command adjust regulators , can be observed. the vsp_rf regulator also includes a current limiter which limits the regulator typically to current of 200 ma rms in normal operation (500 ma in case of short). in case the transmitter output current higher the 200 ma rms is required, vsp_rf regulator cannot be used to supply the transmitter, vsp_rf has to be externally connected to v dd (connection of vsp_rf to supply voltage higher than v dd is not allowed). the voltage drop of the transmitter current is the main source of the AS3911B power dissipation. this voltage drop is composed of drop in the transmitter driver and in the drop on vsp_rf regulator. due to this it is recommended to set regulated voltage using direct command adjust regulators . it results in good power supply rejection ration with relatively low dissipated power due to regulator voltage drop. in power-down mode the vsp_rf regulator is not operating. vsp_rf pin is connected to v dd through 1 k resistor. connection through resistors a ssures smooth power-up of the system and a smooth transition from power-down mode to other operating modes.
AS3911B C 38 ams datasheet: 2014-jun-12 [v1-08] application information vsp_a and vsp_d regulators vsp_a and vsp_d regulators are used to supply the AS3911B analog and digital blocks respec tively. in 3.3 v mode, vsp_a and vsp_d regulator are set to the same regulated voltage as the vsp_rf regulator, in 5 v mode vsp_a and vsp_d regulated voltage is fixed to 3.4 v. the use of vsp_a and vsp_d regulators is obligatory in 5 v mode since analog and digital blocks supplied with these two pins contain low voltage transistors which support maximum supply voltage of 3.6 v. in 3.3 supply mode the use of regulators is strongly recommended in order to improve psrr of analog processing. for low cost applications it is possible to disable the vsp_d regulator and to supply digital blocks through external short between vsp_a and vsp_d (configuration bit vspd_off in the io configuration register 2 . in case vsd_d regulator is disabled vsp_d can alternatively be supplied from v dd (in 3.3 v mode only) in case vsp_a is not more than 300 mv lower than v dd . power-down support block in the power-down mode the regulators are disabled in order to save current. in this mode a low power power-down support block which maintains the vsp_d and vsp_a in below 3.6 v is enabled. typical regulated voltage in this mode is 3.1 v at 5 v supply and 2.2 v at 3 v supply. when 3.3 v supply mode is set the power-down support block is disabled, its output is connected to v dd through 1 k resistor. typical consumption of power-down support block is 600 na at 5 v supply. measurement of supply voltages using direct command measure power supply it is possible to measure v dd and regulated voltages vsp_a, vsp_d, and vsp_rf.
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 39 application information communication to external microcontroller the AS3911B is a slave device and the external microcontroller initiates all communication. communication is performed by a 4-wire serial peripheral interface (spi). the AS3911B asks microcontroller for its attention by sending an interrupt (pin irq). in addition, the microcont roller can use clock signal available on pin mcu_clk when the oscillator is running. serial peripheral interface (spi) while signal /ss is high the spi in terface is in reset, while it is low the spi interface is enabled. it is recommended to keep signal /ss high whenever the spi interface is not in use. mosi is sampled at the falling edge of sclk. all communication is done in blocks of 8 bits (bytes). first two bits of first byte transmitted after high to low transition of /ss define spi operation mode. msb bit is always transmitted firs t (valid for address and data). read and write modes support address auto-incrementing, which means that in case after the address and first data byte some additional data bytes are sent (read), they are written to (read from) addresses incremented by 1. figure 23 defines possible modes. miso output is usually in tristate , it is only driven when output data is available. due to this the mosi and the miso can be externally shorted to create a bidirectional signal. during the time the miso output is in tristate, it is possible to switch on a 10 k pull down by activating option bits miso_pd1 and miso_pd2 in the io configuration register 2 . figure 21: serial data interface (4-wire interface) signal lines name signal signal level description /ss digital input cmos spi enable (active low) mosi digital input cmos serial data input miso digital output with tristate cmos serial data output sclk digital input cmos clock for serial communication
AS3911B C 40 ams datasheet: 2014-jun-12 [v1-08] application information figure 22: signal to microcontroller figure 23 provides information on the spi operation modes. reading and writing of registers is possible in any AS3911B operation mode. fifo operations are possible in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. figure 23: spi operation modes mode mode pattern (communication bits) mode related data mode trailer m1 m0 c5 c4 c3 c2 c1 c0 register write 0 0 a5a4a3a2a1a0 data byte (or more bytes in case of auto-incrementing) register read 0 1 a5 a4 a3 a2 a1 a0 data byte (or more bytes in case of auto-incrementing) fifo load 10000000one or more bytes of fifo data fifo read 10111111one or more bytes of fifo data direct command mode 1 1 c5 c4 c3 c2 c1 c0 mosi miso miso mosi as3911 mosi miso i/o as3911 separate spi input and output signals to microcontr oller bidirectional data io signal to microcontroller
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 41 application information writing of data to addressable registers (write mode) following figures show cases of writing a single byte and writing multiple bytes with auto-incrementing address. after the spi operation mode bits, the address of register to be written is provided. then one or more data bytes are transferred from the spi, always from the msb to the lsb. the data byte is written in register on falling edge of its last clock. in case the communication is terminated by putting /ss high before a packet of 8 bits composing one byte is sent, writing of this register is not performed. in case the register on the defined address does not exist or it is a read only register no write is performed. figure 24: spi communication: wr iting of single byte figure 25: spi communication: writ ing of multiple bytes 00 a 5 a 4 a 3 a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 x x sclk rising edge data is transfered from c sclk falling edge data is sampled data is moved to address a5-a0 /ss rising edge signals end of write mode two leading bits indicate mode /ss sclk mosi 00 a 5 a 4 a 3 a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 x x data is moved to address + n /ss rising edge signals end of write mode two leading bits indicate mode d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 1 d 0 data is moved to address + (n-1) data is moved to address + 1 data is moved to address /ss sclk mosi
AS3911B C 42 ams datasheet: 2014-jun-12 [v1-08] application information reading of data from addressable registers (read mode) after the spi operation mode bits the address of register to be read has to be provided from the msb to the lsb. then one or more data bytes are transferred to miso output, always from the msb to the lsb. as in case of the write mode also the read mode supports auto-incrementing address. mosi is sampled at the falling ed ge of sclk (like shown in the following diagrams), data to be read from the AS3911B internal register is driven to miso pin on rising edge of sclk and is sampled by the master at the falling edge of sclk. in case the register on defined address does not exist all 0 data is sent to miso. figure 26 provides an example for reading of single byte. figure 26: spi communication: reading of single byte loading transmitting data into fifo loading the transmitting data into the fifo is similar to writing data into an addressable registers. difference is that in case of loading more bytes all bytes go to the fifo. spi operation mode bits 10 indicate fifo operations. in case of loading transmitting data into fifo all bits are set to 0. then a bit-stream, the data to be sent (1 to 96 by tes), can be transferred. in case the command is terminated by putting /ss high before a packet of 8 bits composing one byte is sent, writing of that particular byte in fifo is not performed. figure 27 shows how to load the transmitting data into the fifo. 01 a 5 a 4 a 3 a 2 a 1 a 0 x x sclk rising edge data is moved from address /ss rising edge signals end of read mode tw o leading bits indicate mode d 4 d 3 d 2 d 1 d 0 d 7 d 6 tristate tristate sclk rising edge data is transfered from c sclk falling edge data is sampled sclk falling edge data is transfered to c d 5 /ss sclk mosi miso
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 43 application information figure 27: spi communication: loading of fifo reading received data from fifo reading received data from the fifo is similar to reading data from an addressable registers. difference is that in case of reading more bytes they all come from the fifo. spi operation mode bits 10 indicate fifo oper ations. in case of reading the received data from the fifo all bits are set to 1. on the following sclk rising edges the data from fifo appears as in case of read data from addressable registers. in case the command is terminated by putting /ss high before a packet of 8 bits composing one byte is re ad that particular byte is considered unread and will be the first one read in next fifo read operation. figure 28: spi communication: reading of fifo 10000000 1 to 96 bytes x sclk rising edge data is transfered from c sclk falling edge data is sampled 10 pattern indicates fifo mode x start of payload data /ss sclk mosi /ss sclk mosi miso 101111 11 1 to 96 bytes x tristate tristate x sclk rising edge data is transfered from c sclk falling edge data is sampled 10 pattern indicates fifo mode sclk rising edge data is moved from fifo sclk falling edge data is transfered to c
AS3911B C 44 ams datasheet: 2014-jun-12 [v1-08] application information direct command mode direct command mode has no arguments, so a single byte is sent. spi operation mode bits 11 indicate direct command mode. the following six bits define command code, sent msb to the lsb. the command is executed on falling edge of last clock. while execution of some direct commands is immediate, there are others which start a process of certain duration (calibration, measurement). during execution of such commands it is not allowed to start another activity over the spi interface. after execution of such a command is terminated an irq is sent. figure 29: spi communication: direct command direct command chaining direct commands with immediate execution can be followed by another spi mode (read, writ e or fifo) without deactivating /ss signal in between. figure 30: direct command chaining 1 1 c5 c4 c3 c2 c1 c0 x x sclk rising edge data is transfered from c sclk falling edge data is sampled /ss rising edge signals start of command execution two leading one indicate command mode /ss sclk mosi /ss direct command read, write or fifo mode
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 45 application information spi timing figure 31: spi timing figure 32: spi general timing symbol parameter min typ max unit notes general timing (v dd = v dd_io = v dd_d = 3.3 v, temperature 25c) t sclk sclk period 100 ns t sclk =t sclkl +t sclkh, use of shorter sclk period may lead to incorrect operation of fifo t sclkl sclk low 40 *1 ns t sclkh sclk high 40 ns t ssh spi reset (/ss high) 100 ns t ncsl /ss falling to sclk rising 25 ns first sclk pulse t ncsh sclk falling to /ss rising 25 (tbd) ns last sclk pulse t dis data in setup time 10 ns t dih data in hold time 10 ns read timing (v dd = v dd_io = v dd_d = 3.3 v, temperature 25c, c load 50 pf) t dod data out delay 20 ns t dohz data out to high impedance delay 20 ns ... ... ... datai datai datai ... t sclkh t ncsl t sclkl t dis t dih t ncsh /ss mosi miso sclk
AS3911B C 46 ams datasheet: 2014-jun-12 [v1-08] application information figure 33: spi read timing interrupt interface there are three interrupt registers implemented in the AS3911B ( main interrupt register and auxiliary timer and nfc interrupt register and error and wake-up interrupt register ). main interrupt register contains information about six interrupt sources, while two bits reference to interrupt sources detailed in timer and nfc interrupt register and error and wake-up interrupt register . when an interrupt condition is met the source of interrupt bit is set in the main interrupt register and the irq pin transitions to high. the microcontroller then reads the main interrupt register to distinguish between different in terrupt sources. the interrupt registers 0x17, 0x18 and 0x19 are to be read in one attempt. after a particular interrupt register is read, its content is reset to 0. exceptions to this rule are the bits pointing to auxiliary registers. these bits are only cleared when corresponding auxiliary register is read. irq pin transitions to low after the interrupt bit(s) which caused it s transition to high has been read. please note that there may be more than one interrupt bits set in case the microcontr oller did not immediately read the interrupt registers after the irq signal was set and another event causing interrupt occurred. in that case the irq pin transitions to low after the last bit which caused interrupt is read. in case an interrupt from a certai n source is not required it can be disabled by setting correspo nding bit in the mask interrupt registers. in case of masking a certain interrupt source the interrupt is not produced, but the source of interrupt bit is still set in interrupt registers. ... ... ... datai ... datao datao t dod t dohz /s s mosi miso sclk
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 47 application information figure 34: irq output fifo water level and fifo status registers the AS3911B contains a 96 byte fifo. in case of transmitting the control logic shifts the data, which was previously loaded by the external microcontrol ler to the framing block and further to the transmitter. during reception, the demodulated data is stored in the fifo and the external microcontroller can download received data once reception was terminated. transmit and receive capabilities of the AS3911B are not limited by the fifo size due to a fifo water level interrupt system. during transmission an interrupt is sent (irq due to fifo water level in the main interrupt register ) when the content of data in the fifo passes from ( water level + 1 ) to water level and the complete transmit frame has not been loaded in the fifo yet. the external microcontroller can now add more data in the fifo. the same stands for the reception: when the number of received bytes passes from ( water level - 1 ) to water level an interrupt is sent to inform the external controller that data has to be downloaded from fifo in order not to lose receive data due to fifo overflow. during transmission water level irq is additionally set in case all transmission bytes have not be en written in fifo yet and if number of bytes written into fifi o is lower than water level. in this case an irq is sent when number of bytes in fifo drops below 4. it is important to note that fi fo irq is not produced while spi is active in fifo load or read mode. due to this the fifo loading/reading rate has to be higher than tx/rx bit rate, once fifo loading/reading is finished the /ss pin has to be pulled to v dd (logic remains in fifo load/read mode as long as /ss remains low). in case controller knows that the receive data frame is smaller than the fifo size the water level interrupt does not have to be served. in such case the water level interrupt can be masked. the external controller has to serve the fifo faster than data is transmitted or received. using sc lk frequency which is at least double than the actual receive or transmit bit rate is recommended. there are two settings of the fifo water level available for receive and transmit in the io configuration register 1 . after data reception is terminated the external microcontroller needs to know how much data is still stored in the fifo: this information is available in the fifo status register 1 and fifo status register 2 which displays number of bytes in the fifo name signal signal level description irq digital output cmos interrupt output pin
AS3911B C 48 ams datasheet: 2014-jun-12 [v1-08] application information which were not read out. fifo status register 1 can also be read while reception and transmission processes are active to get info about current number of byte s in fifo. in that case user has to take in account that rx/tx process is going on and that the number of data bytes in fifo may have already changed by the time the reading of register is finished. the fifo status register 2 additionally contains two bits which i n d i c a t e t h a t t h e f i f o w a s n o t c o r r e c t l y s e r ve d d u r i n g r e c e p t i o n or transmission process (fifo overflow and fifo underflow). fifo overflow is set when too mu ch data is written in fifo. in case this bit is set during rece ption the external controller did not react on time on water level irq and more than 96 bytes were written in the fifo. the received data is of course corrupted in such a case. during transmission this means that controller has written more data than fifo size. the data to be transmitted was corrupted. fifo underflow is set when data was read from empty fifo. in case this bit is set during reception the external controller read more data than was actually received. during transmission this means that controller has failed to provide the quantity of data defined in number of transmitted bytes registers on time. pin mcu_clk pin mcu_clk may be used as clock source for the external microcontroller. depending on the operation mode either a low frequency clock (32 khz) from the rc oscillator or the clock signal derived from crystal oscillator is available on pin mcu_clk. the mcu_clk output pin is controlled by bits out_c1 , out_cl0 and lf_clk_off in the io configuration register 1 . bits out_cl enable the use of pin mcu_clk as clock source and define the division for the case the crystal oscillator is running (13.56 mhz, 6.78 mhz and 3.39 mhz are available). bit lf_clk_off controls the use of low frequency clock (32 khz) in case the crystal oscillator is not running. by default configuration, which is defined at power-up, the 3.39 mhz clock is selected and the low frequency clock is enabled. in case the transparent mode (see stream mode and transparent mode on page 140 ) is used the use of mcu_clk is mandatory since clock which is synchronous to the field carrier frequency is needed to implement receive and transmit framing in the external controller. the use of mcu_clk is recommended also for the case where the in ternal framing is used. using mcu_clk as the microcontroller clock source generates noise which is synchronous to the reader carrier frequency and is therefore filtered out by the receiver while using some other incoherent clock source may produce noise which perturbs the reception. use of mcu_clk is also better for emc compliance.
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 49 application information direct commands figure 35: list of direct commands command code (hex) command comments command chaining interrupt after termination operation mode (1) c1 set default puts the AS3911B in default state (same as after power-up) no no all c2, c3 clear stops all activities and clears fifo yes no en c4 transmit with crc starts a transmit sequence using automatic crc generation yes no en, tx_en c5 transmit without crc starts a transmit sequence without automatic crc generation yes no en, tx_en c6 transmit reqa transmits reqa command (iso14443a mode only) yes no en, tx_en c7 transmit wupa transmits wupa command (iso14443a mode only) yes no en, tx_en c8 nfc initial field on performs initial rf collision avoidance and switch on the field yes yes en (2) c9 nfc response field on performs response rf collision avoidance and switch on the field yes yes en (2) ca nfc response field on with n=0 performs response rf collision avoidance with n=0 and switch on the field yes yes en (2) cb go to normal nfc mode accepted in nfcip-1 active communication bit rate detection mode yes no cc analog preset presets rx and tx configuration based on state of mode definition register and bit rate definition register yes no all d0 mask receive data receive after this command is ignored yes no en, rx_en
AS3911B C 50 ams datasheet: 2014-jun-12 [v1-08] application information d1 unmask receive data receive data following this command is normally processed (this command has priority over internal mask receive timer) yes no en, rx_en d2 see note (3) not used d3 measure amplitude amplitude of signal present on rfi inputs is measured, result is stored in a/d converter output register no yes en d4 squelch performs gain reduction based on the current noise level no no en, rx_en d5 reset rx gain clears the current squelch setting and loads the manual gain reduction from receiver configuration register 4 no no en (4) d6 adjust regulators adjusts supply regulators according to the current supply voltage level no yes en (5) d7 calibrate modulation depth starts sequence which activates the tx, measures the modulation depth and adapts it to comply with the specified modulation depth no yes en d8 calibrate antenna starts the sequence to adjust parallel capacitances connected to trimx pins so that the antenna lc tank is in resonance no yes en d9 measure phase measurement of phase difference between the signal on rfo and rfi no yes en da clear rssi clears rssi bits and restarts the measurement yes no en dc transparent mode enter in transparent mode no no en dd calibrate capacitive sensor calibrates capacitive sensor no yes see note (6) command code (hex) command comments command chaining interrupt after termination operation mode (1)
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 51 application information note(s) and/or footnote(s): 1. the operation mode column in the above table defines which operation control register bits have to be set in order to accept a particular command. 2. after termination of this command i_cat or i_cac irq is sent. 3. was ad convert in the as3910. 4. called clear squelch in the as3910. 5. this command is not accepted in case the external definition of the regulated voltage is selected in the regulator voltage control register (bit reg_s is set to high). 6. accepted in all modes in case cs_mcal =0 ( capacitive sensor control register ), it is recommended to execute this command in power-down mode. 7. accepted in all modes, it is recommended to execute this command in power-down mode. 8. accepted only in the initial nf c active target communication mode. 9. called check antenna resonance in the as3910. 10. called measure rf in the as3910. de measure capacitance performs capacitor sensor measurement no yes see note (7) df measure power supply no yes en e0 start general purpose timer yes no en e1 start wake-up timer yes no all except wu e2 start mask-receive timer yes no see note (8) e3 start no-response timer yes no en, rx_en fc test access enable /w to test registers yes no all other fx reserved for test other codes not used command code (hex) command comments command chaining interrupt after termination operation mode (1)
AS3911B C 52 ams datasheet: 2014-jun-12 [v1-08] application information set default this direct command puts the AS3911B in the same state as power-up initialization. all regist ers are initialized to the default state. the only exception are io configuration register 1 , io configuration register 2 and operation control register which are not affected by set default command and are only set to default state at power-up. please note that results of different calibration and adjust commands are also lost. this direc t command is accepted in all operating modes. in case this command is sent while en (bit 7 of the operation control register ) is not set fifo and fifo status registers are not cleared. direct command chaining is not allowed since this command clears all registers. irq due to termination of direct command is not produced. clear this direct command stops all current activities (transmission or reception), clears fifo, clears fifo status registers and stops all timers except wake-up timer (in case bit nrt_emv in the general purpose and no-response timer control register is set to one, the no-response timer is not stopped). it also clears collision and interrupt registers. this command has to be sent first in a sequence preparing a tr ansmission before writing data to be transmitted in fifo (exc ept in case of direct commands transmit reqa and transmit wupa ). this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is possible. irq due to termination of direct command is not produced. transmit commands all transmit commands ( transmit with crc , transmit without crc , transmit reqa and transmit wupa ) are only accepted in case the transmitter is enabled (bit tx_en is set). before sending commands transmit with crc and transmit without crc direct command clear has to be sent, followed by definition of number of transmit ted bytes and writing data to be transmitted in fifo. direct commands transmit reqa and transmit wupa are used to transmit iso14443a commands reqa and wupa respectively. sending command clear before these two commands is not necessary. direct command chaining is possible. irq due to termination of direct command is not produced.
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 53 application information nfc field on commands these commands are used to perform the rf collision avoidance and switch the field on in case no collision was detected. the collision avoidance threshold defined in the external field detector threshold register is used to observe the rf_in inputs and to determine whether there is some other device, which is emitting the 13.56 mhz field, present close to the AS3911B antenna. in case collision is not detected the reader field is switched on automatically (bit tx_en in the operation control register is set) and an irq with i_cat flag in timer and nfc interrupt register is sent after minimum guard time defined by the nfcip-1 stan dard to inform the controller that message transmission usin g a transmit command can be initiated. in case a presence of external field is detected an irq with i_cac flag is sent. in such case a tr ansmission cannot be performed, nfc field on command has to be repeated as long as collision is not detected any more. command nfc initial field on performs initial collision avoidance according to nfcip-1 standard; number n is defined by bits nfc_n1 and nfc_n0 in auxiliary definition register . command nfc response field on performs response collision avoidance according to nfcip-1 standard; number n is defined by bits nfc_n1 and nfc_n0 in auxiliary definition register . command nfc response field on with n=0 , performs response collision avoidance where n is 0. implemented active delay time is on lower nfcip-1 specification limit, since the actual active delay time will also include detection of the fiel d deactivation, controller processing delay and sending the nfc field on command. figure 36: direct command nfc initial field on start rf on t rfw t irfg n x t rfw t idt
AS3911B C 54 ams datasheet: 2014-jun-12 [v1-08] application information figure 37: direct command nfc response field on figure 38: timing parameters of nfc field on commands this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency and amplitude are stable. go to normal nfc mode this command is used to transition from nfc target bit rate detection mode to normal mode . additionally it copies the content of the nfcip bit rate detection display register to the bit rate definition register and correctly sets the bit tr_am in the auxiliary definition register . analog preset this command is used to preset receiver and transmitter configuration based on state of bit rate definition register and bit rate definition register . in case of sub-carrier bit stream or bpsk bit stream mode, this command should not be used. the list of configuration bits that are preset is given in figure 39 . symbol parameter value unit note t idt initial delay time 4096 /fc nfc initial field on t rwf rf waiting time 512 /fc t irfg initial guard time >5 ms nfc initial field on t adt active delay time 768 /fc nfc response field on t arfg active guard time 1024 /fc nfc response field on start rf on t rfw t arfg n x t rfw t adt
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 55 application information figure 39: register preset bits bit bit name function address 02 h : operation control register 5rx_chn 1: one channel enabled nfcip-1 active communication (both initiator and target) 3tx_en 0: disable tx operation nfcip-1 active communication (both initiator and target) note : in case of any target mode or nfcip-1 initiator mode bit tx_en is set to 0 to disable transmitter in case it was enabled. in nfcip-1 mode the switching on of the transmitter field is controlled by dedicated commands. address 05 h : iso14443a and nfc 106kb/s settings register 5 nfc_f0 1: add sb (f0) and len byte during tx and skip sb (f0) byte during tx nfcip-1 active communication (both initiator and target) address 09 h : auxiliary definition register 5tr_am tx modulation type (depends on mode definition and tx bit rate) 0: ook iso144443a, nfcip-1 106 kb/s (both initiator and target), nfc forum type 1 tag 1: am iso144443b, felica, nfcip-1 212 kb/s and 424 kb/s 4en_fd enable external field detector with peer detection threshold 0: all modes except nfcip-1 active communication 1: nfcip-1 active communication (both initiator and target) address 0a h : receiver configuration register 1 7ch_sel 0: enable am channel nfcip-1 active communication (both initiator and target) 6amd_sel am demodulator select (depend on rx bit rate) 0: peak detector all rx bit rates equal or below fc/16 (848 kb/s) 1: mixer all vhbr rx bit rates (fc/8 and fc/4) 5lp2 low pass control (depends on mode definition and rx bit rate) (see figure 15 ) 4lp1 3lp0 2h200 first and third stage zero setting (depends on mode definition and rx bit rate) (see figure 15 ) 1h80 0z12k address 0c h : receiver configuration register 3 1lim clip output of 1 st and 2 nd stage 0: all modes except nfcip-1 active communication 1: nfcip-1 active communication (both initiator and target) 0rg_nfc forces gain reduction in 2 nd and 3 rd gain stage 0: all modes except nfcip-1 active communication 1: nfcip-1 active communication (both initiator and target)
AS3911B C 56 ams datasheet: 2014-jun-12 [v1-08] application information mask receive data and unmask receive data after the direct command mask receive data the signal rx_on , which enables the rssi and agc operation of the receiver (see also receiver ) is forced to low, processing of the receiver output by the receive data framing block is disabled. this command is useful to mask receiver and receive framing from processing the data when there is actually no input and only a noise would be processed (for example in case where a transponder processing time after receiving a command from the reader is long). masking of receive is al so possible using mask receive timer. actual masking is a logical or of the two mask receive processes. the direct command unmask receive data is enabling normal processing of the received data (signal rx_on is set high to enable the rssi and agc operation), the receive data framing block is enabled. a common use of this command is to enable again the receiver operation after it was masked by the command mask receive data . in case mask receive timer is running while command unmask receive data is received, reception is enabled, mask receive timer is reset. the commands mask receive data and unmask receive data are only accepted when the receiver is enabled (bit rx_en is set). direct command chaining is possible. irq due to termination of direct command is not produced. measure amplitude this command measures the amplitude on the rfi inputs and stores result in the a/d converter output register . when this command is executed the transmitter and amplitude detector are enabled, the output of the amplitude detector is multiplexed to the a/d converter input (the a/d converter is in absolute mode). the amplitud e detector conversion gain is 0.6 v inpp / v out . one lsb of the a/d converter output represents 13.02 mv pp on the rfi inputs. a 3 v pp signal, which is maximum allowed level on each of the two rfi inputs, results in 1.8 v output dc voltage and would produce a value of 1110 0110b on the a/d converter output. duration time: 25 s max. this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is not possible. irq due to termination of dire ct command is produced after command execution is terminated. squelch this direct command is intended to avoid demodulation problems of transponders which produce a lot of noise during data processing. it can also be used in a noisy environment. the operation of this comm and is explained in squelch on page 23 .
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 57 application information duration time: 500 s max. this command is only accepted when the transmitter and the receiver are operating. command is actually executed only in case signal rx_on is low. direct command chaining is not possible. irq due to termination of direct command is not produced. reset rx gain this command initializes the ag c, squelch and rssi block. sending this command stops a squelch process in case it is going on, clears the current squelch setting and loads the manual gain reduction from receiver configuration register 4 . this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is possible. irq due to termination of direct command is not produced. adjust regulators when this command is sent the power supply level of v dd is measured in maximum load conditions and the regulated voltage reference is set 250 mv below this measured level to assure maximum possible stable regulated supply ( see power supply system on page 35. ). using this command increases the system pssr. at the beginning of executio n of this command, both the receiver and transmitter are switched on to have the maximum current consumption, the regula tors are set to the maximum regulated voltage (5.1 v in case of 5 v supply and 3.4 v in case of 3.3 v supply mode). after 300 s vsp_rf is compared to v dd , in case vsp_rf is not at least 250 mv lower the regulator setting is reduced for one step (120 mv in case of 5 v supply and 100 mv in case of 3.3 v supply mode ) and measurement is done after next 300 s. procedure is repeated until vsp_rf drops at least 250 mv below v dd or until minimum regulated voltage (3.9 v in case of 5 v supply and 2.4 v in case of 3.3 v supply mode) is reached. duration time: 5 ms max. this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. this command is not accepted in case the external definition of the regulated voltage is selected in the regulator voltage control register (bit reg_s is set to h) direct command chaining is not possible. irq due to termination of dire ct command is produced after command execution is terminated.
AS3911B C 58 ams datasheet: 2014-jun-12 [v1-08] application information calibrate modulation depth starts a patent pending sequence, which activates the transmission, measures the modu lation depth and adapts it to comply with the modulation depth specified in the am modulation depth control register . when calibration procedure is finished result is displayed in the am modulation depth display register . please refer to am modulation depth: definition and calibration on page 135 for details about setting the am modulation dept h and running this command. duration time: 275 s max. this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is not possible. irq due to termination of dire ct command is produced after command execution is terminated. calibrate antenna sending this command starts a sequence which adjusts the parallel capacitances connected to trimx pins so that the antenna lc tank is in resonance. see antenna tuning on page 138 for details. duration time: 250 s max. this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. measure phase this command measures the phase difference between the signals on the rfo outputs and the signals on the rfi inputs and stores the result in the a/d converter output register . during execution of the direct command measure phase the transmitter and phase detector are enabled, the phase detector output is multiplexed on the input of a/ d converter, which is set in relative mode. since the a/d converter range is from 1/6 vsp_a to 5/6 vsp_a the actual phase detector range is from 30o to 150o. values below 30o result in ff h while values above 150o result in 00 h . 1 lsb of the a/d conversion output represents 0.13% of carrier freque ncy period (0.468). the result of a/d conversion is in case of 90o phase shift in the middle of range (1000 0000b or 0111 1111b). value higher than 1000 0000b means that phase detector output voltage is higher than vsp_a/2, which corresponds to case with phase shift lower than 90o. in the opposite case, when the phase shift is higher than 90o, the result of a/d conversion is lower than 0111 1111b. for example, the phase difference of 135o depicted in figure 18 results in 0.75 vsp_a, result stored in a/d converter is 31 d (1f h ).
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 59 application information the phase measurement result can be calculating using the following formulas: duration time: 25 s max. this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is not possible. irq due to termination of dire ct command is produced after command execution is terminated. clear rssi the receiver automatically clears the rssi bits in the receiver state display register and starts to measure the rssi of the received signal when the signal rx_on is asserted. since the rssi bits store peak value (peak-hold type) eventual variation of the receiver input signal will not be followed (this may happen in case of long message or test procedure). the direct command clear rssi clears the rssi bits in the receiver state display register, the rssi measurement is restarted (in case of course rx_on is still high). this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is possible. irq due to termination of direct command is not produced. transparent mode enter in the transparent mode. the transparent mode is entered on the rising edge of signal /ss and is maintained as long as signal /ss is kept high. see transparent mode on page 59 for more details. this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. calibrate capacitive sensor this command calibrates the capacitive sensor. see capacitive sensor on page 14 for more details. duration time: 3 ms max. this command is executed in case capacitive sensor automatic calibration mode is set (all bits cs_mcal in the capacitive sensor control register are set to 0). in order to avoid interference with xtal oscillator and reader magnetic field it strongly recommended to use this command in power-down mode only. direct command chaining is not possible. irq due to termination of dire ct command is produced after command execution is terminated. [] () [] 0 : 180 150 0 . 120 * ) 0 . 255 / ) _ 0 . 255 ( 0 . 30 deg _ : 150 30 255 : 30 0 = ? + = < < = dec result angle u rees angle dec result ? ? ?
AS3911B C 60 ams datasheet: 2014-jun-12 [v1-08] application information measure capacitance this command performs the capacitance measurement. see capacitive sensor on page 14 for more details. duration time: 250 s max. in order to avoid interference with xtal oscillator and reader magnetic field it strongly recommended to use this command in power-down mode only. direct command chaining is not possible. irq due to termination of dire ct command is produced after command execution is terminated. measure power supply this command performs the power supply measurement. configuration bits mpsv1 and mpsv0 of the regulator voltage control register define which power supply is measured (v dd , vsp_a, vsp_d and vsp_rf can be measured). result of measurement is stored in the a/d converter output register . during the measurement the selected supply input is connected to a 1/3 resistive divider output of which is multiplexed to a/d converter in absolute mode. due to 1/3 division one lsb represents 23.438 mv. duration time: 25 s max. this command is accepted in case en (bit 7 of the operation control register ) is set and xtal oscillator frequency is stable. direct command chaining is not possible. irq due to termination of dire ct command is produced after command execution is terminated. start timers see timers on page 29 . test access the AS3911B does not contain any dedicated test pins. a direct command test access is used to enable rw access of test registers and entry in different test modes. pins csi and cso are used as test pins. test mode entry and access to test registers test registers are not part of no rmal spi register address space. after sending a direct command test access , test regisers can be accessed using normal read /write register spi command. access to test register is possible in a chained command sequence where first command test access is sent, followed by read/write access to test registers using auto increment feature. after spi interface reset (ss toggle) the content of test registers is kept. test register are set to default state at power-up and by sending commands set default and clear test registers.
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 61 application information figure 40: analog test and observation register note(s) and/or footnote(s): 1. default setting is set at power-up and after commands set default and clear test registers figure 41: test access register - tana signal selection of csi and cso pins test address 01 h : analog test and observation register type: rw bit name default function comments 7tana_7 0do not change 6tana_6 0do not change 5tana_5 0do not change 4not used 3tana_3 0 see figure 41 these test modes are also intended for observation in normal mode. several modes of this register are also available when analog test mode is not set. 2tana_2 0 1tana_1 0 0tana_0 0 tana_ pin csi pin cso 3 2 1 0 pin type functionality pin type functionality comment 0 0 0 1 ao analog output of am channel (before digitizer) do digital output of am channel (after digitizer) normal operation 0 0 1 0 ao analog output of pm channel (before digitizer) do digital output of pm channel (after digitizer) normal operation 0 0 1 1 ao analog output of am channel (before digitizer) ao analog output of pm channel (before digitizer) normal operation 0 1 0 0 do digital output of am channel (after digitizer) do digital output of pm channel (after digitizer) normal operation 0 1 0 1 ao analog signal after first stage ao analog signal after second stage normal operation pm channel if enabled, am if pm is not enabled
AS3911B C 62 ams datasheet: 2014-jun-12 [v1-08] application information registers the 6-bit register addresses below are defined in the hexadecimal notation. the possible address range is from 00 h to 3f h . there are two types of registers implemented in the AS3911B: configuration registers and displa y registers. the configuration registers are used to configure the AS3911B. they can be written and read through the spi (rw). the display registers are read only (ro); they contain information about the AS3911B internal state. registries are set to their default state at power-up and after sending direct command set default . the only exceptions are the io configuration register 1 and the io configuration register 2 which are only set to default state at power-up. configuration bits of these two registries are related to hardware configuration which is in most cases not going to change during the operation. figure 42: register description 1 0 0 1 do channel selection from logic do collision avoidance detector output collision avoidance detectors are enabled 1 0 1 0 do digital tx modulation signal do select pm analog part of channel selection address[hex] content comment type io configuration registers 00 io configuration register 1 set to default state only at power-up rw 01 io configuration register 2 rw operation control and mode definition registers 02 operation control register set to default state only at power-up rw 03 mode definition register 04 bit rate definition register rw tana_ pin csi pin cso 3 2 1 0 pin type functionality pin type functionality comment
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 63 application information configuration registers 05 iso14443a and nfc 106kb/s settings register rw 06 iso14443b settings register 1 rw 07 iso14443b and felica settings register rw 08 stream mode definition register rw 09 auxiliary definition register rw 0a receiver configuration register 1 rw 0b receiver configuration register 2 rw 0c receiver configuration register 3 rw 0d receiver configuration register 4 rw timer definition registers 0e mask receive timer register rw 0f no-response timer register 1 rw 10 no-response timer register 2 rw 11 general purpose and no-response timer control register rw 12 general purpose timer register 1 rw 13 general purpose timer register 2 rw interrupt and associated reporting registers 14 mask main interrupt register rw 15 mask timer and nfc interrupt register rw 16 mask error and wake-up interrupt register rw 17 main interrupt register r 18 timer and nfc interrupt register r 19 error and wake-up interrupt register r 1a fifo status register 1 r 1b fifo status register 2 r 1c collision display register r address[hex] content comment type
AS3911B C 64 ams datasheet: 2014-jun-12 [v1-08] application information definition of number of transmitted bytes 1d number of transmitted bytes register 1 rw 1e number of transmitted bytes register 2 rw nfcip bit rate detection display register 1f nfcip bit rate detection display register r a/d converter output register 20 a/d converter output register r antenna calibration registers 21 antenna calibration control register rw 22 antenna calibration target register rw 23 antenna calibration display register r am modulation depth and antenna driver registers 24 am modulation depth control register rw 25 am modulation depth display register r 26 rfo am modulated level definition register rw 27 rfo normal level definition register rw external field detector threshold registers 29 external field detector threshold register rw regulator registers 2a regulator voltage control register rw 2b regulator and timer display register r receiver state display registers 2c rssi display register r 2d gain reduction state register r capacitive sensor registers 2e capacitive sensor control register rw 2f capacitive sensor display register r auxiliary display register 30 auxiliary display register r address[hex] content comment type
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 65 application information wake-up registers 31 wake-up timer control register rw 32 amplitude measurement configuration register rw 33 amplitude measurement reference register rw 34 amplitude measurement auto-averaging display register r 35 amplitude measurement display register r 36 phase measurement configuration register rw 37 phase measurement reference register rw 38 phase measurement auto-averaging display register r 39 phase measurement display register r 3a capacitance measurement configuration register rw 3b capacitance measurement reference register rw 3c capacitance measurement auto-averaging display register r 3d capacitance measurement display register r ic identity register 3f ic identity register r address[hex] content comment type
AS3911B C 66 ams datasheet: 2014-jun-12 [v1-08] application information io configuration register 1 figure 43: io configuration register 1 note(s) and/or footnote(s): 1. default setting is set at power-up only. address 00 h : io configuration register 1 type: rw bit name default function comments 7single 0 1: only one rfo driver will be used choose between single and differential driving of antenna 6rfo2 0 0: rfo1, rfi1 1: rfo2, rfi2 choose which output driver and which input will be used in case of single driving 5fifo_lr 0 0: 64 1: 80 fifo water level for receive 4fifo_lt 0 0: 32 1: 16 fifo water level for transmit 3osc 1 0: 13.56 mhz xtal 1: 27.12 mhz xtal selector for crystal oscillator use of vhbr is only possible with 27.12 mhz xtal 2 out_cl1 0 out_cl1 out_cl0 mcu_clk selection of clock frequency on mcu_clk output in case xtal oscillator is running. in case of 11 mcu_clk output is permanently low. 0 0 3.39 mhz 0 1 6.78 mhz 1 out_cl0 0 1 0 13.56 mhz 11disabled 0lf_clk_off 0 1: no lf clock on mcu_clk by default the 32 khz lf clock is present on mcu_clk output when xtal oscillator is not running and the mcu_clk output is not disabled.
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 67 application information io configuration register 2 figure 44: io configuration register 2 note(s) and/or footnote(s): 1. default setting is set at power-up only. address 01 h : io configuration register 2 type: rw bit name default function comments 7sup3 v0 0: 5 v supply 1: 3.3 v supply 5 v supply, range: 4.1 v to 5.5 v 3.3 v supply, range: 2.4 v to 3.6 v min. 3.0v for vhbr 6vspd_off0 1: disable vsp_d regulator used for low cost applications. when this bit is set: at 3 v or 5 v supply vsp_d and vsp_a shall be shorted externally at 3.3 v applications vsp_d can alternatively be supplied from v dd in case vsp_a is not more than 300 mv lower then v dd 5not used 4miso_pd20 1: pull-down on miso, when /ss is low and miso is not driven by the AS3911B 3miso_pd10 1: pull-down on miso when /ss is high 2io_180 1: increase miso driving level in case of 1.8 v v dd_io 1not used 0slow_up0 1: slow ramp at tx on 10s 10% to 90%, for b
AS3911B C 68 ams datasheet: 2014-jun-12 [v1-08] application information operation control register figure 45: operation control register note(s) and/or footnote(s): 1. default setting is set at power-up only. address 02 h : operation control register type: rw bit name default function comments 7en 0 1: enables oscillator and regulator (ready mode) 6rx_en 0 1: enables rx operation 5rx_chn 0 0: both, am and pm, channels enabled 1: one channel enabled in case only one rx channel is enabled, selection is done by the receiver configuration register 1 bit ch_sel 4rx_man 0 0: automatic channel selection 1: manual channel selection in case both rx channels are enabled, it chooses the method of channel selection, manual selection is done by the receiver configuration register 1 bit ch_sel 3tx_en 0 1: enables tx operation this bit is automatically set by nfc field on commands and reset in nfc active communication modes after transmission is finished 2wu 0 1: enables wake-up mode according to settings in wake-up timer control register 1 not used 0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 69 application information mode definition register figure 46: mode definition register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. figure 47: initiator operation modes note(s) and/or footnote(s): 1. in case an operation mode which is not suppor ted is selected, the tx/rx operation is disabled. address 03 h : mode definition register type: rw bit name default function comments 7targ 0 0: initiator 1: target 6om3 0 refer to initiator operation modes and target operation modes selection of operation mode. different for initiator and target mode. 5om2 0 4om1 0 3om0 1 20 not used 10 0nfc_ar 0 automatic start of response rf collision avoidance sequence initiator operation modes om3 om2 om1 om0 comment 0 0 0 0 nfcip-1 active communication 0 0 0 1 iso14443a 0 0 1 0 iso14443b 00 1 1felica 0 1 0 0 nfc forum type 1 tag (topaz) 1 1 1 0 sub-carrier stream mode 11 1 1bpsk stream mode other combinations not used
AS3911B C 70 ams datasheet: 2014-jun-12 [v1-08] application information figure 48: target operation modes note(s) and/or footnote(s): 1. in case an operation mode which is not suppor ted is selected, the tx/rx operation is disabled. bit rate definition register figure 49: bit rate definition register note(s) and/or footnote(s): 1. default setting is se t at power-up and after set default command. 2. automatically loaded by direct command go to normal nfc mode . target operation modes om3 om2 om1 om0 comment 0 0 0 0 nfcip-1 active communication, bit rate detection mode 0 0 0 1 nfcip-1 active communication, normal mode other combinations not used address 04 h : bit rate definition register type: rw bit name default function comments 7tx_rate3 0 refer to bit rate coding selects bit rate for tx 6tx_rate2 0 5tx_rate1 0 4tx_rate0 0 3rx_rate3 0 selects bit rate for rx in case selected protocol allows different bit rates for rx and tx 2rx_rate2 0 1rx_rate1 0 0rx_rate0 0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 71 application information figure 50: bit rate coding note(s) and/or footnote(s): 1. in case a bit rate which is not supported is selected, the tx/rx operation is disabled. iso14443a and nfc 106kb/s settings register figure 51: iso14443a and nfc 106kb/ s settings register bit rate coding rate3 rate2 rate1 rate0 bit rate [kbit/s] comment 0 0 0 0 fc/128 (~106) 0 0 0 1 fc/64 (~212) 0 0 1 0 fc/32 (~424) 0 0 1 1 fc/16 (~848) 0 1 0 0 fc/8 (~1695) vhbr tx is supported only for iso14443b mode vhbr rx is supported only for fc/8 and fc/4 0 1 0 1 fc/4 (~3390) 0 1 1 0 fc/2 (~6780) other combinations not used address 05 h : iso14443a and nfc 106kb/s settings register type: rw bit name default function comments 7 no_tx_par 0 1: no parity bit is generated during tx data stream is taken from fifo, transmit has to be done using command transmit without crc 6 no_rx_par 0 1: receive without parity and crc when set to 1 received bi t stream is put in the fifo, no parity and crc detection is done 5nfc_f0 0 1: support of nfcip-1 transport frame format add sb (f0) and len bytes during tx and skip sb (f0) byte during rx in nfc active communication mode 4p_len3 0 refer to iso14443a modulation pulse width modulation pulse width; defined in number of 13.56 mhz clock periods. 3p_len2 0 2p_len1 0 1p_len0 0
AS3911B C 72 ams datasheet: 2014-jun-12 [v1-08] application information note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. 2. no_tx_par and no_rx_par are used to send and re ceive custom frames like mifare? classic frames. figure 52: iso14443a modulation pulse width 0antcl 0 1: iso14443 anticollision frame has to be set to 1 when iso14443a bit oriented anticollision frame is sent iso14443a modulation pulse width p_len3 p_len2 p_len1 p_len0 pulse width in number of 1/fc for different bit rates fc/128 fc/64 fc/32 fc/16 01 1 1 42 01 1 0 41 20 01 0 1 40 21 0 1 0 0 39 22 13 0 0 1 1 38 21 12 8 0 0 1 0 37 20 11 7 0 0 0 1 36 19 10 6 00 0 0 35 18 9 5 11 1 1 34 17 8 4 11 1 0 33 16 7 3 11 0 1 32 15 6 2 11 0 0 31 14 5 10 1 1 30 13 10 1 0 29 12 10 0 1 28 10 0 0 27 address 05 h : iso14443a and nfc 106kb/s settings register type: rw bit name default function comments
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 73 application information iso14443b settings register 1 figure 53: iso14443b settings register note(s) and/or footnote(s): 1. default setting is se t at power-up and after set default command. 2. start/stop bit omission for tx can be implemented by using stream mode. address 06 h : iso14443b settings register 1 type: rw bit name default function comments 7egt2 0 egt2 egt1 egt0 number of egt egt time defined in number of etu 000 0 6egt1 0 001 1 . . . . . . . . 5egt0 0 110 6 111 6 4 sof_0 0 0 10 etu, 1 11 etu sof, number of etu with logic 0 (10 or 11) 3 sof_1 0 0 2 etu, 1 3 etu sof, number of etu with logic 1 (2 or 3) 2eof 0 0 10 etu, 1 11 etu eof, number of etu with logic 0 (10 or 11) 1half 1: sof 10.5, 2.5, eof: 10.5 sets sof and eof settings in middle of specification 0 rx_st_om 1: start/stop bit omission for rx sof= fixed to 10 low - 2 high, eof not defined, put in fifo last full byte (2)
AS3911B C 74 ams datasheet: 2014-jun-12 [v1-08] application information iso14443b and felica settings register figure 54: iso14443b and felica settings register note(s) and/or footnote(s): 1. default setting is se t at power-up and after set default command. 2. detection of eof requires larger tolerance range for bit rate s with only one sub-carrier frequency period per bit (fc/16 and higher). due to this it is not possible to distingu ish between eof with 11 and 12 etu and setti ng this bit has no impact on eof detectio n. figure 55: minimum tr1 codings note(s) and/or footnote(s): 1. tr1 is defined in number of su b-carrier cycles, therefore at vhbr the absolute time becomes shorter. address 07 h : iso14443b and felica settings register type: rw bit name default function comments 7 tr1_1 0 refer to minimum tr1 coding 6 tr1_0 0 5no_sof 0 1: no sof picc to pcd according to iso14443-3 chapter 7.10.3.3 support of b 4no_eof 0 1: no eof picc to pcd according to iso14443-3 chapter 7.10.3.3 3eof_12 0 0: picc eof 10 to 11 etu 1: picc eof 10 to 12 etu support of b (2) 2phc_th 0 1: increased tolerance of phase change detection 1f_p1 0 00: 48 01: 64 10: 80 11: 96 felica preamble length (valid also for nfcip-1 active communication bit rates 242 and 484 kb/s) 0f_p0 0 minimum tr1 coding tr1_1 tr1_0 minimum tr1 for a picc to pcd bit rate fc / 128 > fc / 128 0 0 80 / fs 80 / fs 0 1 64 / fs 32 / fs 1 0 not used not used 1 1 not used not used
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 75 application information stream mode definition register figure 56: stream mode definition register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. figure 57: sub-carrier frequency definition fo r sub-carrier and bpsk stream mode address 08 h : stream mode definition register type: rw bit name default function comments 70 6scf1 0refer to sub-carrier frequency definition for sub-carrier and bpsk stream mode sub-carrier frequency definition for sub-carrier and bpsk stream mode 5scf0 0 4scp1 0 scp1 scp0 number of pulses number of sub-carrier pulses in report period for sub-carrier and bpsk stream mode 001 (bpsk only) 01 2 3scp0 0 10 4 11 8 2stx2 0refer to definition of time period for stream mode tx modulator control definition of time period for tx modulator control (for sub-carrier and bpsk stream mode) 1stx1 0 0stx0 sub-carrier frequency definition for sub-carrier and bpsk stream mode scf1 scf0 sub-carrier mode bpsk mode 0 0 fc/64 (212 khz) fc/16 (848 khz) 0 1 fc/32 (424 khz) fc/8 (1695 khz) 1 0 fc/16 (848 khz) fc/4 (3390 khz) 11fc/8 (1695 khz)not used
AS3911B C 76 ams datasheet: 2014-jun-12 [v1-08] application information figure 58: definition of time period for stream mode tx modulator control definition of time period for stream mode tx modulator control stx2 stx1 stx0 time period 0 0 0 fc/128 (106 khz) 001 fc/64 (212 khz) 010 fc/32 (424 khz) 011 fc/16 (848 khz) 1 0 0 fc/8 (1695 khz) 1 0 1 fc/4 (3390 khz) 1 1 0 fc/2(6780 khz) 111 not used
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 77 application information auxiliary definition register figure 59: auxiliary definition register note(s) and/or footnote(s): 1. default setting is se t at power-up and after set default command. 2. receive without crc is done auto matically in case reqa and wupa commands are sent using direct commands transmits reqa command and transmits wupa command , respectively, and in case anticollis ion is performed by setting bit antcl. 3. automatic preset of the tr_am 4. 0: ook ? iso144443a, nfcip-1 106 kb/s, nfc forum type 1 tag 5. 1: am ? iso144443b, felica, nfcip-1 212 and 424 kb/s 6. while en_fd is set, and field detected in ap2p mode, this time r is reserved for internal use. address 09 h : auxiliary definition register type: rw bit name default function comments 7no_crc_rx 0 1: receive without crc valid for all protocols, for iso14443a reqa, wupa and anticollision receive without crc is done automatically (2) 6crc_2_fifo 0 1: make crc check, but put crc bytes in fifo and add them to number of receive bytes needed for emv compliance 5tr_am 0 0: ook, 1: am set automatically by command analog preset , can be modified by register write, has to be defined for transparent and bit stream mode tx (3) 4en_fd 0 1: enable external field detector external field detector with peer detection threshold is activated. preset for nfcip-1 active communication mode 3ook_hr 0 1: puts rfo driver in three-state during ook modulation valid for all protocols using ook modulation (also in transparent mode) 2rx_tol 1 1: bpsk fc/32: more tolerant bpsk decoder for bit rate fc/32, iso14443a fc/128, nfcip-1 fc/128: more tolerant processing of first byte 1 nfc_n1 0 definition on n for direct commands nfc initial field on and nfc response field on 0nfc_n0 0
AS3911B C 78 ams datasheet: 2014-jun-12 [v1-08] application information receiver configuration register 1 figure 60: receiver configuration register 1 note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 0a h : receiver configuration register 1 (filter and demodulator settings) type: rw bit name default function comments 7ch_sel 0 0: enable am channel 1: enable pm channel in case only one rx channel is enabled in the operation control register it defines which channel is enabled. in case both channels are enabled and manual channel selection is active, it defines which channel is used for receive framing. 6 amd_sel 0 0: peak detector 1: mixer am demodulator type select, vhbr automatic preset to mixer 5lp2 0 low pass control ( figure 13 ) for automatic and other recommended filter settings, refer to figure 15 . 4lp1 0 3lp0 0 2 h200 0 first and third stage zero setting (see figure 14 ) 1h80 0 0z12k 0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 79 application information receiver configuration register 2 figure 61: receiver configuration register 2 note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 0b h : receiver configuration register 2 type: rw bit name default function comments 7rx_lp 0 1: low power receiver operation 6lf_op 0 0: differential lf operation 1: lf input split (rfi1 to am channel, rfi2 to pm channel) 5lf_en 0 1: lf signal on receiver input 4agc_en 1 1: agc is enabled 3 agc_m 1 0: agc operates on first eight sub-carrier pulses 1: agc operates during complete receive period 2 agc_alg 0 0: algorithm with preset is used 1: algorithm with reset is used algorithm with preset is recommended for protocols with short sof (like iso14443a fc/128) 1sqm_dyn 1 1: automatic squelch activation after end of tx activated 18.88 s after end of tx, terminated with mask receive timer expire 0 pmix_cl 0 0: rfo 1: internal signal pm demodulator mixer clock source, in single mode internal signal is always used
AS3911B C 80 ams datasheet: 2014-jun-12 [v1-08] application information receiver configuration register 3 figure 62: receiver configuration register 3 note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 0c h : receiver configuration register 3 (1st stage gain settings) type: rw bit name default function comments 7 rg1_am2 1 gain reduction/boost in first gain stage of am channel. 0: full gain 1-6: gain reduction 2.5 db per step (15 db total) 7: boost +5.5 db 6 rg1_am1 1 5 rg1_am0 0 4 rg1_pm2 1 gain reduction/boost in first gain stage of pm channel. 0: full gain 1-6: gain reduction 2.5 db per step (15 db total) 7: boost +5.5 db 3 rg1_pm1 1 2 rg1_pm0 0 1lim 0 1: clip output of 1 st and 2 nd stage signal clipped to 0.6 v, preset for nfcip-1 active communication mode 0rg_nfc 0 1: forces gain reduction in 2 nd and 3 rd gain stage to -6 db and maximum comparator window preset for nfcip-1 active communication mode. after clearing this bit, receiver must be restarted.
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 81 application information receiver configuration register 4 figure 63: receiver configuration register 4 note(s) and/or footnote(s): 1. default setting is se t at power-up and after set default command. 2. sending of direct command reset rx gain is necessary to load the value of this re gister into agc, squelch, and rssi block. address 0d h : receiver configuration register 4 (2 nd and 3 rd stage gain settings) type: rw bit name default function comments 7 rg2_am3 0 am channel : gain reduction in second and third stage and digitizer values from 0 h to a h are used. other values are not used. settings 1 h to 4 h reduce gain by increasing the digitizer window in 3db steps, values from 5 h to a h additionally reduce the gain in 2 nd and 3 rd gain stage also in 3 db steps. 6 rg2_am2 0 5 rg2_am1 0 4 rg2_am0 0 3 rg2_pm3 0 pm channel : gain reduction in second and third stage and digitizer values from 0 h to a h are used. other values are not used. settings 1 h to 4 h reduce gain by increasing the digitizer window in 3db steps, values from 5 h to a h additionally reduce the gain in 2 nd and 3 rd gain stage also in 3 db steps. 2 rg2_pm2 0 1 rg2_pm1 0 0 rg2_pm0 0
AS3911B C 82 ams datasheet: 2014-jun-12 [v1-08] application information mask receive timer register figure 64: mask receive timer register note(s) and/or footnote(s): 1. default setting is se t at power-up and after set default command. 2. in nfcip-1 bit rate detection mode, the cl ock of the mask receiv e timer is additionally divided by eight (one count is 512/fc) to cover range up to ~9.6 ms. no-response timer register 1 figure 65: no-response timer register 1 note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 0e h : mask receive timer register type: rw bit name default function comments 7mrt7 0 defined in steps of 64/fc (4.72 s). range from 256/fc (~18.88 s) to 16320/fc (~1.2 ms) timeout = mrt<7:0> * 64/fc timeout (0 mrt<7:0> 4) = 4 * 64/fc (18.88 s) in nfcip-1 bit rate detection mode one step is 512/fc (37.78 s) defines time after end of tx during which receiver output is masked (ignored). for the case of iso14443a 106 kbit/s the mask receive timer is defined according to pcd to picc frame delay time definition, where mrt<7:0> define number of n/2 steps. minimum mask receive time of 18.88 s covers the transients in receiver after end of transmission. 6mrt6 0 5mrt5 0 4mrt4 0 3mrt3 1 2mrt2 0 1mrt1 0 0mrt0 0 address 0f h : no-response timer register 1 type: rw bit name default function comments 7nrt15 0 no-response timer definition msb bits defined in steps of 64/fc (4.72 s). range from 0 to 309 ms in case bit nrt_step in general purpose and no-response timer control register is set the step is changed to 4096/fc defines timeout after end of tx. in case this timeout expires without detecting a response a no-response interrupt is sent. in nfc mode the no response timer is started only when external field is detected all 0: no-response timer is not started. no-response timer is reset and restarted with start no-response timer direct command. 6nrt14 0 5nrt13 0 4nrt12 0 3nrt11 0 2nrt10 0 1nrt9 0 0nrt8 0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 83 application information no-response timer register 2 figure 66: no-response timer register 2 note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. general purpose and no-response timer control register figure 67: general purpose and no-response timer control register address 10 h : no-response timer register 2 type: rw bit name default function comments 7nrt7 0 no-response timer definition lsb bits 6nrt6 0 5nrt5 0 4nrt4 0 3nrt3 0 2nrt2 0 1nrt1 0 0nrt0 0 address 11 h : general purpose and no-response timer control register type: rw bit name default function comments 7gptc2 0 defines the timer trigger source. refer to timer trigger source . 6gptc1 0 5gptc0 0 40 30 20
AS3911B C 84 ams datasheet: 2014-jun-12 [v1-08] application information note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. figure 68: timer trigger source 1 nrt_emv 0 1: emv mode of no-response timer 0nrt_step 0 0: 64/fc 1: 4096/fc selects the no-response timer step. timer trigger source gptc2 gptc1 gptc0 trigger source 00 0 no trigger source, start only with direct command start general purpose timer . 0 0 1 end of rx (after eof) 01 0start of rx 01 1 end of tx in nfc mode, when general purpose timer expires the field is switched off 10 0 not used 10 1 11 0 11 1 address 11 h : general purpose and no-response timer control register type: rw bit name default function comments
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 85 application information general purpose timer register 1 figure 69: general purpose timer register 1 note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. general purpose timer register 2 figure 70: general purpose timer register 2 note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 12 h : general purpose timer register 1 type: rw bit name default function comments 7gpt15 general purpose timeout definition msb bits defined in steps of 8/fc (590 ns) range from 590 ns to 38,7 ms 6gpt14 5gpt13 4gpt12 3gpt11 2gpt10 1gpt9 0gpt8 address 13 h : general purpose timer register 2 type: rw bit name default function comments 7gpt7 general purpose timeout definition lsb bits defined in steps of 8/fc (590 ns) range from 590 ns to 38,7 ms 6gpt6 5gpt5 4gpt4 3gpt3 2gpt2 1gpt1 0gpt0
AS3911B C 86 ams datasheet: 2014-jun-12 [v1-08] application information mask main interrupt register figure 71: mask main interrupt register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. mask timer and nfc interrupt register figure 72: mask timer and nfc interrupt register address 14 h : mask main interrupt register type: rw bit name default function comments 7m_osc 0 mask irq when oscillator frequency is stable 6 m_wl 0 mask irq due to fifo water level 5 m_rxs 0 mask irq due to start of receive 4 m_rxe 0 mask irq due to end of receive 3 m_txe 0 mask irq due to end of transmission 2 m_col 0 mask irq due to bit collision 10 not used 00 address 15 h : mask timer and nfc interrupt register type: rw bit name default function comments 7m_dct 0 mask irq due to termination of direct command 6 m_nre 0 mask irq due to no-response timer expire 5 m_gpe 0 mask irq due to general purpose timer expire 4 m_eon 0 mask irq due to detection of external field higher than target activation level 3m_eof 0 mask irq due to detection of external field drop below target activation level
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 87 application information note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. mask error and wake-u p interrupt register figure 73: mask error and wake-up interrupt register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. 2 m_cac 0 mask irq due to detection of collision during rf collision avoidance 1 m_cat 0 mask irq after minimum guard time expire 0m_nfct 0 mask irq when in target mode the initiator bit rate was recognized address 16 h : mask error and wake-up interrupt register type: rw bit name default function comments 7 m_crc 0 mask irq due to crc error 6 m_par 0 mask irq due to parity error 5 m_err2 0 mask irq due to soft framing error 4 m_err1 0 mask irq due to hard framing error 3m_wt 0 mask irq due to wake-up interrupt 2 m_wam 0 mask wake-up interrupt due to amplitude measurement 1 m_wph 0 mask wake-up interrupt due to phase measurement. 0m_wcap 0 mask wake-up interrupt due to capacitance measurement address 15 h : mask timer and nfc interrupt register type: rw bit name default function comments
AS3911B C 88 ams datasheet: 2014-jun-12 [v1-08] application information main interrupt register figure 74: main interrupt register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. 2. after main interrupt register has been read, its content is set to 0, except for bits 1 and 0, which are set to 0 after corresponding interrupt register is read. address 17 h : main interrupt register type: r bit name default function comments 7i_osc irq when oscillator frequency is stable set after oscillator is started by setting operation control register bit en . 6 i_wl irq due to fifo water level set during receive, informing that fifo is almost full and has to be read out. set during transmit, informing that fifo is almost empty and that additional data has to be sent. 5 i_rxs irq due to start of receive 4 i_rxe irq due to end of receive 3 i_txe irq due to end of transmission 2 i_col irq due to bit collision 1 i_tim irq due to timer or nfc event details are in timer and nfc interrupt register 0i_err irq due to error and wake-up timer details are in error and wake-up interrupt register
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 89 application information timer and nfc interrupt register figure 75: timer and nfc interrupt register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. 2. after timer and nfc interrupt register has been read, its content is set to 0. address 18 h : timer and nfc interrupt register type: r bit name default function comments 7i_dct irq due to termination of direct command 6i_nre irq due to no-response timer expire 5i_gpe irq due to general purpose timer expire 4i_eon irq due to detection of external field higher than target activation level 3i_eof irq due to detection of external field drop below target activation level 2i_cac irq due to detection of collision during rf collision avoidance an external field was detected during rf collision avoidance 1i_cat irq after minimum guard time expire an external field was not detected during rf collision avoidance, field was switched on, irq is sent after minimum guard time according to nfcip-1 0i_nfct irq when in target mode the initiator bit rate was recognized
AS3911B C 90 ams datasheet: 2014-jun-12 [v1-08] application information error and wake-up interrupt register figure 76: error and wake-up interrupt register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0 2. after error and wake-up interrupt register has been read, its content is set to 0 address 19 h : error and wake-up interrupt register type: r bit name default function comments 7 i_crc crc error 6i_par parity error 5 i_err2 soft framing error framing error which does not result in corrupted rx data 4 i_err1 hard framing error framing error which results in corrupted rx data 3i_wt wake-up interrupt timeout after execution of start wake-up timer command in case option with irq at every timeout is selected 2i_wam wake-up interrupt due to amplitude measurement result of amplitude measurement was am larger than reference 1i_wph wake-up interrupt due to phase measurement. result of phase measurement was pm larger than reference 0 i_wcap wake-up interrupt due to capacitance measurement result of capacitance measurement was cm larger than reference
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 91 application information fifo status register 1 figure 77: fifo status register 1 note(s) and/or footnote(s): 1. at power-up and after direct commands set default and clear , content of this register is set to 0. address 1a h : fifo status register 1 type: r bit name default function comments 7 6fifo_b6 number of bytes (binary coded) in the fifo which were not read out valid range is from 0 (000 0000b) to 96 (110 0000b) 5fifo_b5 4fifo_b4 3fifo_b3 2fifo_b2 1fifo_b1 0fifo_b0
AS3911B C 92 ams datasheet: 2014-jun-12 [v1-08] application information fifo status register 2 figure 78: fifo status register 2 note(s) and/or footnote(s): 1. at power-up and after direct commands set default and clear , content of this register is set to 0. 2. if fifo is empty, the value of register fifo status register 1 (0x1a h ) is 0x00, register bits fifo_ncp , fifo_lb2 , fifo_lb1 and fifo_lb0 in register block 0x1b h are cleared. correct procedure for fifo read is to read both fifo status register 1 & 2" and then read fifo. second register values need to be saved in mcu, if non-complete bytes are in fifo. address 1b h : fifo status register 2 type: r bit name default function comments 7 6fifo_unf fifo underflow set when more bytes then actual content of fifo were read 5 fifo_ovr fifo overflow 4 fifo_ncp last fifo byte is not complete 3fifo_lb2 number of bits in last fifo byte in case it was not complete (fifo_npc=1) in case of incomplete byte the lsb part is valid 2fifo_lb1 1fifo_lb0 0 np_lb parity bit is missing in last byte this is a framing error
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 93 application information collision display register figure 79: collision display register note(s) and/or footnote(s): 1. at power-up and after direct commands set default and clear , content of this register is set to 0. address 1c h : collision display register (for iso14443a and nfcip-1bit rate fc/128 rx) type: r bit name default function comments 7c_byte3 number of full bytes before the bit collision happened. the collision display register range covers iso14443a anticollision command. in case collision (or framing error which is interpreted as collision) happens in a longer message, the collision display register is not set. 6c_byte2 5c_byte1 4c_byte0 3c_bit2 number of bits before the collision in the byte where the collision happened 2c_bit1 1c_bit0 0 c_pb collision in parity bit this is an error, reported in case it is the first collision detected
AS3911B C 94 ams datasheet: 2014-jun-12 [v1-08] application information number of transmitted bytes register 1 figure 80: number of transmitted bytes register 1 note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. number of transmitted bytes register 2 figure 81: number of transmitted bytes register 2 note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. 2. if anctl bit is set while card is in id le state and nbtx is not 000, then i_par will be triggered during wupa direct command is issued. address 1d h : number of transmitted bytes register 1 type: rw bit name default function comments 7ntx12 0 number of full bytes to be transmitted in one command, msb bits maximum supported number of bytes is 8191 6ntx11 0 5ntx10 0 4ntx9 0 3ntx8 0 2ntx7 0 1ntx6 0 0ntx5 0 address 1e h : number of transmitted bytes 2 type: rw bit name default function comments 7ntx4 0 number of full bytes to be transmitted in one command, msb bits maximum supported number of bytes is 8191 6ntx3 0 5ntx2 0 4ntx1 0 3ntx0 0 2nbtx2 number of bits in the split byte 000 means that there is no split byte (all bytes all complete) applicable for iso14443a: ? bit oriented anticollision frame in case last byte is split byte ? tx is done without parity bit generation 1nbtx1 0nbtx0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 95 application information nfcip bit rate detection display register figure 82: nfcip bit rate detection display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. a/d converter output register figure 83: a/d converter output register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. address 1f h : nfcip bit rate detection display register type: r bit name default function comments 7nfc_rate3 refer to bit rate coding this register stores result of automatic bit rate detection in the nfcip-1 active communication bit rate detection mode 6nfc_rate2 5nfc_rate1 4nfc_rate0 3 not used 2 1 0 address 20 h : a/d converter output register type: r bit name default function comments 7ad7 displays result of last a/d conversion. 6ad6 5ad5 4ad4 3ad3 2ad2 1ad1 0ad0
AS3911B C 96 ams datasheet: 2014-jun-12 [v1-08] application information antenna calibration control register figure 84: antenna calibration control register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 21 h : antenna calibration control register type: rw bit name defau lt function comments 7trim_s0 0: lc trim switches are defined by result of calibrate antenna command 1: lc trim switches are defined by bits tre_x written in this register defines source of driving switches on trimx pins 6tre_30msb lc trim switches are defined by data written in this register in case trim_s=1. a bit set to 1 switch on transi stor on trim1_x and trim2_x pin. 5 tre_2 0 4 tre_1 0 3tre_00lsb 2 1 0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 97 application information antenna calibration target register figure 85: antenna calibration target register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. antenna calibration display register figure 86: antenna calibration display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. address 22 h : antenna calibration target register type: rw bit name default function comments 7act7 1 define target phase for calibrate antenna direct command 6act6 0 5act5 0 4act4 0 3act3 0 2act2 0 1act1 0 0act0 0 address 23 h : antenna calibration display register type: r bit name default function comments 7tri_3 msb this register stores result of calibrate antenna command. lc trim switches are defined by data written in this register in case trim_s = 0. a bit set to 1 indicates that corresponding transistor on trim1_x and trim2_x pin is switched on. 6tri_2 5tri_1 4tri_0 lsb 3 tri_err 1: antenna calibration error set when calibrate antenna sequence was not able to adjust resonance 2 not used 1 0
AS3911B C 98 ams datasheet: 2014-jun-12 [v1-08] application information am modulation depth control register figure 87: am modulation depth control register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 24 h : am modulation depth control register type: rw bit name default function comments 7am_s 0 0: am modulated level is defined by bits mod5 to mod0. level is adjusted automatically by calibrate modulation depth command 1: am modulated level is defined by bits dram7 to dram0. 6mod5 0msb see application notes for details about am modulation level definition. 5mod4 0 4mod3 0 3mod2 0 2mod1 0 1mod0 0lsb 0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 99 application information am modulation depth display register figure 88: am modulation depth display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. rfo am modulated level definition register figure 89: rfo am modulated level definition register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 25 h : am modulation depth display register type: r bit name default function comments 7md_7 msb displays result of calibrate modulation depth command. antenna drivers are composed of 8 binary weighted segments. bit md_x set to one indicates that this particular segment will be disabled during am modulated state. in case of error all 1 value is set. 6md_6 5md_5 4md_4 3md_3 2md_2 1md_1 0md_0 lsb address 26 h : rfo am modulated level definition register type: rw bit name default function comments 7dram7 0msb antenna drivers are composed of 8 binary weighted segments. setting a bit dram to 1 will disable corresponding segment during am modulated state in case am_s bit is set to 1. 6dram6 0 5dram5 0 4dram4 0 3dram3 0 2dram2 0 1dram1 0 0dram0 0lsb
AS3911B C 100 ams datasheet: 2014-jun-12 [v1-08] application information rfo normal level definition register figure 90: rfo normal level de finition register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. applying value ffh to the register 27h will put the drivers in tristate. external field detector threshold register figure 91: external field detector threshold register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 27 h : rfo normal level definition register type: rw bit name default function comments 7droff7 02 ohm antenna drivers are composed of 8 binary weighted segments. setting a bit droff to 1 will disable corresponding segment during normal non-modulated operation. the tx drivers are made up of 8 segments. binary weighted from 2 ohm to 256ohm. by setting register 0x27 to 0xc0 you disable the 2 ohm and 4 ohm segments. 6droff6 04 ohm 5droff5 08 ohm 4droff4 016 ohm 3droff3 032 ohm 2droff2 064 ohm 1 droff1 0 128 ohm 0 droff0 0 256 ohm address 29 h : external field detector threshold register type: rw bit name default function comments 7not used 6 trg_l2 0 peer detection threshold msb peer detection threshold. refer to peer detection threshold as seen on rfi1 input . 5trg_l1 1 4 trg_l0 1 peer detection threshold lsb 3 rfe_t3 0 collision avoidance threshold msb collision avoidance threshold. refer to collision avoidance threshold as seen on rfi1 input . 2rfe_t2 0 1rfe_t1 1 0 rfe_t0 1 collision avoidance threshold lsb
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 101 application information figure 92: peer detection threshold as seen on rfi1 input peer detection threshold as seen on rfi1 input trg_l2 trg_l1 trg_l0 target peer detection threshold voltage [mv pp on rfi1] 000 75 001 105 010 150 011 205 100 290 101 400 110 560 111 800
AS3911B C 102 ams datasheet: 2014-jun-12 [v1-08] application information figure 93: collision avoidance threshold as seen on rfi1 input collision avoidance threshold as seen on rfi1 input rfe_3 rfe_2 rfe_1 rfe_0 typical collision avoidance threshold voltage [mv pp on rfi1] 0000 75 0001 105 0010 150 0011 205 0100 290 0101 400 0110 560 0111 800 1000 25 1001 33 1010 47 1011 64 1100 90 1101 125 1110 175 1111 250
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 103 application information regulator voltage control register figure 94: regulator voltage control register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 2a h : regulated voltage control register type: rw bit name default function comments 7reg_s 0 0: regulated voltages are defined by result of adjust regulators command 1: regulated voltages are defined by rege_x bits written in this register defines mode of regulator voltage setting. 6 rege_3 0 msb external definition of regulated voltage. refer to regulated voltage for definition. in 5 v mode vsp_d and vsp_a regulators are set to 3.4 v 5 rege _2 0 4 rege _1 0 3rege _0 0lsb 2mpsv1 0 00: v dd 01: vsp_a 10: vsp_d 11: vsp_rf define source of direct command measure power supply . 1mpsv0 0 0
AS3911B C 104 ams datasheet: 2014-jun-12 [v1-08] application information regulator and timer display register figure 95: regulator and timer display register note(s) and/or footnote(s): 1. at power-up and after set default command, regulated voltage is set to maximum 3.4v. address 2b h : regulator and timer display register type: r bit name default function comments 7 reg_3 msb this register displays actual regulated voltage setting. refer to regulated voltage for definition. 6reg_2 5reg_1 4 reg_0 lsb 3 2 gpt_on 1: general purpose timer is running 1 nrt_on 1: no-response timer is running 0mrt_on 1: mask receive timer is running
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 105 application information figure 96: regulated voltages regulated voltage reg_3 rege_3 reg_2 rege_2 reg_1 rege_1 reg_0 rege_0 typical regulated voltage [v] 5 v mode 3.3 v mode 1111 5.1 3.4 1110 4.98 3.3 1101 4.86 3.2 1100 4.74 3.1 1011 4.62 3.0 1010 4.50 2.9 1001 4.38 2.8 1000 4.26 2.7 0111 4.14 2.6 0110 4.02 2.5 0101 3.90 2.4 other combinations not used
AS3911B C 106 ams datasheet: 2014-jun-12 [v1-08] application information rssi display register figure 97: rssi display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. 2. bit 0x30[7] indicates which rssi value is use in the logic for internal use. address 2c h : rssi display register type: r bit name default function comments 7 rssi_am_3 msb stores peak value of am channel rssi measurement. automatically cleared at beginning of transponder message and with clear rssi command. 6 rssi_am_2 5 rssi_am_1 4 rssi_am_0 lsb 3 rssi_pm_3 msb stores peak value of pm channel rssi measurement. automatically cleared at beginning of transponder message and with clear rssi command. 2 rssi_pm_2 1 rssi_pm_1 0 rssi_pm_0 lsb
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 107 application information figure 98: rssi table rssi table rssi_3 rssi_2 rssi_1 rssi_0 typical signal on rfi1 [mv rms ] 0000 20 0001 >20 0010 >27 0011 >37 0100 >52 0101 >72 0110 >99 0111 >136 1000 >190 1001 >262 1010 >357 1011 >500 1100 >686 1101 >950 1110 not used 1111
AS3911B C 108 ams datasheet: 2014-jun-12 [v1-08] application information gain reduction state register figure 99: gain reduction state register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. address 2d h : gain reduction state register type: r bit name default function comments 7 gs_am_3 msb actual gain reduction of second stage of am channel (including register gain reduction, squelch and agc) 6gs_am_2 5gs_am_1 4 gs_am_0 lsb 3 gs_pm_3 msb actual gain reduction of second stage of pm channel (including register gain reduction, squelch and agc) 2 gs_pm_2 1 gs_pm_1 0 gs_pm_0 lsb
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 109 application information capacitive sensor control register figure 100: capacitive sensor control register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. address 2e h : capacitive sensor control register type: rw bit name default function comments 7cs_mcal4 0 manual calibration value all 0 value enables automatic calibration mode binary weighted, step 0.1 pf, max 3.1 pf 6cs_mcal3 0 5cs_mcal2 0 4cs_mcal1 0 3cs_mcal0 0 2cs_g2 0 000: 2.8 v/pf 001: 6.5 v/pf 010: 1.1 v/pf 100: 0.5 v/pf 110: 0.35 v/pf other: not used capacitor sensor gain typical values 1cs_g1 0 0cs_g0 0
AS3911B C 110 ams datasheet: 2014-jun-12 [v1-08] application information capacitive sensor display register figure 101: capacitive sensor display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. auxiliary display register figure 102: auxiliary display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. address 2f h : capacitive sensor display register type: r bit name default function comments 7cs_cal4 capacitive sensor calibration value binary weighted, step 0.1 pf, max 3.1 pf 6cs_cal3 5cs_cal2 4cs_cal1 3cs_cal0 2cs_cal_end 1: calibration ended 1cs_cal_err 1: calibration error 0 address 30 h : auxiliary display register type: r bit name default function comments 7a_cha 0: am 1: pm currently selected channel 6 efd_o external field detector output 5tx_on 1: transmission is active 4 osc_ok 1: x-tal oscillation is stable indication that x-tal oscillator is active and its output is stable 3rx_on 1: receive coder is enabled 2rx_act 1: receive coder is receiving a message 1nfc_t 1: external field detector is active in peer detection mode 0en_ac 1: external field detector is active in rf collision avoidance mode
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 111 application information wake-up timer control register figure 103: wake-up timer control register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. figure 104: typical wake-up time address 31 h : wake-up timer control register type: rw bit name default function comments 7wur 0 0: 100 ms 1: 10 ms wake-up timer range 6wut2 0 refer to typical wake-up time wake-up timer timeout value 5wut1 0 4wut0 0 3wto 0 1: irq at every timeout 2wam 0 1: at timeout perform amplitude measurement irq if difference larger than am 1wph 0 1: at timeout perform phase measurement irq if difference larger than pm 0wcap 0 1: at timeout perform capacitance measurement irq if difference larger than cm typical wake-up time wut2 wut1 wut0 100 ms range (wur=0) 10 ms range (wur=1) 0 0 0 100 ms 10 ms 0 0 1 200 ms 20 ms 0 1 0 300 ms 30 ms 0 1 1 400 ms 40 ms 1 0 0 500 ms 50 ms 1 0 1 600 ms 60 ms 1 1 0 700 ms 70 ms 1 1 1 800 ms 80 ms
AS3911B C 112 ams datasheet: 2014-jun-12 [v1-08] application information amplitude measurement configuration register figure 105: amplitude measurement configuration register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 32 h : amplitude measurement configuration register type: rw bit name default function comments 7am_d3 0 definition of am (difference to reference which triggers interrupt) 6am_d2 0 5am_d1 0 4am_d0 0 3 am_aam 0 0: exclude the irq measurement 1: include the irq measurement include/exclude the measurement which causes irq (having difference > am to reference) in auto-averaging 2am_aew1 0 00: 4 01: 8 10: 16 11: 32 define weight of last measurement result for auto-averaging 1am_aew2 0 0am_ae 0 1: use amplitude measurement auto-averaging as reference
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 113 application information amplitude measurement reference register figure 106: amplitude measurement reference register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. amplitude measurement auto-averaging display register figure 107: amplitude measurement auto-averaging display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. address 33 h : amplitude measurement reference register type: rw bit name default function comments 7am_ref7 0 6am_ref6 0 5am_ref5 0 4am_ref4 0 3am_ref3 0 2am_ref2 0 1am_ref1 0 0am_ref0 0 address 34 h : amplitude measurement auto-averaging display register type: r bit name default function comments 7 am_aad7 6 am_aad6 5 am_aad5 4 am_aad4 3 am_aad3 2 am_aad2 1 am_aad1 0 am_aad0
AS3911B C 114 ams datasheet: 2014-jun-12 [v1-08] application information amplitude measurement display register figure 108: amplitude measurement display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. address 35 h : amplitude measurement display register type: r bit name default function comments 7am_amd7 6am_amd6 5am_amd5 4am_amd4 3am_amd3 2am_amd2 1am_amd1 0am_amd0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 115 application information phase measurement configuration register figure 109: phase measurement configuration register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 36 h : phase measurement configuration register type: rw bit name default function comments 7 pm_d3 0 definition of pm (difference to reference which triggers interrupt) 6 pm_d2 0 5 pm_d1 0 4 pm_d0 0 3 pm_aam 0 0: exclude the irq measurement 1: include the irq measurement include/exclude the measurement which causes irq (having difference > pm to reference) in auto-averaging 2 pm_aew1 0 00: 4 01: 8 10: 16 11: 32 define weight of last measurement result for auto-averaging 1 pm_aew0 0 0 pm_ae 0 1: use phase measurement auto-averaging as reference
AS3911B C 116 ams datasheet: 2014-jun-12 [v1-08] application information phase measurement reference register figure 110: phase measurement reference register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. phase measurement auto-averaging display register figure 111: phase measurement auto-averaging display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. address 37 h : phase measurement reference register type: rw bit name default function comments 7 pm_ref7 0 6 pm_ref6 0 5 pm_ref5 0 4 pm_ref4 0 3 pm_ref3 0 2 pm_ref2 0 1 pm_ref1 0 0 pm_ref0 0 address 38 h : phase measurement auto-averaging display register type: r bit name default function comments 7 pm_aad7 6 pm_aad6 5 pm_aad5 4 pm_aad4 3 pm_aad3 2 pm_aad2 1 pm_aad1 0 pm_aad0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 117 application information phase measurement display register figure 112: phase measurement display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. address 39 h : phase measurement display register type: r bit name default function comments 7pm_amd7 6pm_amd6 5pm_amd5 4pm_amd4 3pm_amd3 2pm_amd2 1pm_amd1 0pm_amd0
AS3911B C 118 ams datasheet: 2014-jun-12 [v1-08] application information capacitance measurement configuration register figure 113: capacitance measurement configuration register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. address 3a h : capacitance measurement configuration register type: rw bit name default function comments 7cm_d3 0 definition of cm (difference to reference which triggers interrupt) 6cm_d2 0 5cm_d1 0 4cm_d0 0 3cm_aam 0 0: exclude the irq measurement 1: include the irq measurement include/exclude the measurement which causes irq (having difference > cm to reference) in auto-averaging 2cm_aew1 0 00: 4 01: 8 10: 16 11: 32 define weight of last measurement result for auto-averaging 1cm_aew0 0 0cm_ae 0 1: use capacitance measurement auto-averaging as reference
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 119 application information capacitance measurement reference register figure 114: capacitance measurement reference register note(s) and/or footnote(s): 1. default setting is set at power-up and after set default command. capacitance measurement auto-averaging display register figure 115: capacitance measurement auto-averaging display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. address 3b h : capacitance measurement reference register type: rw bit name default function comments 7cm_ref7 0 6cm_ref6 0 5cm_ref5 0 4cm_ref4 0 3cm_ref3 0 2cm_ref2 0 1cm_ref1 0 0cm_ref0 0 address 3c h : capacitance measurement auto-averaging display register type: r bit name default function comments 7 cm_aad7 6 cm_aad6 5 cm_aad5 4 cm_aad4 3 cm_aad3 2 cm_aad2 1 cm_aad1 0 cm_aad0
AS3911B C 120 ams datasheet: 2014-jun-12 [v1-08] application information capacitance measurement display register figure 116: capacitance measurement display register note(s) and/or footnote(s): 1. at power-up and after set default command, content of this register is set to 0. ic identity register figure 117: ic identity register address 3d h : capacitance measurement display register type: r bit name default function comments 7cm_amd7 6cm_amd6 5cm_amd5 4cm_amd4 3cm_amd3 2cm_amd2 1cm_amd1 0cm_amd0 address 3f h : ic identity register type: r bit name default function comments 7ic_type4 code for AS3911B: 00001 5 bit ic type code 6ic_type3 5ic_type2 4ic_type1 3ic_type0 2ic_rev2 010 3 bit ic revision code, 001 is code for silicon r2.0, 010 is code for silicon r3.0, 011 is code for silicon r3.3 1ic_rev1 0ic_rev0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 121 application information power-up sequence at power-up, the AS3911B enters the power-down mode. the content of all registers is set to the default state. 1. firstly, the microcontroller after a power-up must correctly configure the two io configuration registers. the content of these two registers defines operation options related to hardware (power supply mode, xtal type, use of mcu_clk clock, antenna operation mode). 2. configure the regulators. it is recommended to use direct command adjust regulators to improve the system psrr. 3. if implementing the lc tank tuning, then send the direct command calibrate antenna . 4. if using the am modulation (iso14443b for example), then set the modula tion depth in the am modulation depth control register and send the command calibrate modulation depth . 5. the AS3911B is now ready to operate. reader operation to begin with, the operation mode and data rate have to be configured by writing the mode definition register and bit rate definition register . additionally, the receiver and transmitter operation options related to operation mode have to be defined. this is done automatically by sending the direct command analog preset . if more options are required apart from those defined by analog preset , then such options must be additionally set by writing the appropriate registers. next, the ready mode has to be entered by setting the bit en of the operation control register . in this mode the oscillator is started and the regulators are enabled. when the oscillator operation is stable, an interrupt is sent. before sending any command to a transponder, the transmitter and receiver have to be en abled by setting the bits rx_en and tx_en . rfid protocols usually require that the reader field is turned on for a while before sending the first command (5 ms for iso14443). general purpose ti mer can be used to count this time.
AS3911B C 122 ams datasheet: 2014-jun-12 [v1-08] application information in case reqa or wupa has to be sent this is simply done by sending appropriate direct command otherwise the following sequence has to be followed: 1. send the direct command clear 2. define the number of transmitted bytes in the number of transmitted bytes register 1 and number of transmitted bytes register 2 3. write the bytes to be transmitted in the fifo 4. send the direct command transmit with crc or transmit without crc (whichever is appropriate) 5. when all the data is transmi tted an interrupt is sent to inform the microcontroller that the transmission is finished (irq due to end of transmission) after the transmission is executed, the AS3911B receiver automatically starts to observe the rfi inputs to detect a transponder response. the rssi and agc (in case it is enabled) are started. the framing block pr ocesses the sub-carrier signal from receiver and fills the fifo with data. when the reception is finished and all the data is in the fifo an interrupt is sent to the microcontroller (irq due to end of receive), additionally the fifo status register 1 and fifo status register 2 display the number of bytes in the fifo so the microcontroller can proceeded with downloading the data. in case there was an error or bit collision detected during reception, an interrupt with appropriate flag is sent. microcontroller has to take appropriate action. transmit and receive in case data packet is longer than fifo: i n c a s e a d a t a p a c k e t i s l o n g e r t h a n f i f o t h e s e q u e n c e e x p l a i n e d above is modified. before transmit the fifo is fill ed. during transmit an interrupt is sent when remaining number of bytes is lower than the water level (irq due to fifo water level). the microcontroller in turn adds more data in the fifo. when all the data is transmitted an interrupt is sent to inform the microcontroller that transmission is finished. during reception situation is simila r. in case the fifo is loaded with more data than the receive water level, an interrupt is sent and the microcontroller in turn reads the data from the fifo. when reception is finished an interrupt is sent to the microcontroller (irq due to end of receive), additionally the fifo status register 1 and fifo status register 2 display the number of bytes in the fifo which are still to be read out. anticollision C iso 14443a note: for this section, it is assu med that there are more than one iso/iec 14443a picc in the readers rf field and all are compatible to iso/iec 14443 up to level 4. this section highlights on a procedure of performing anticollision with AS3911B for iso14443a tags. after an iso14443 type a tag enters in the reader field, the reader has
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 123 application information to perform a selection process which brings it into the protocol state in which the actual application implemented in the tag can be executed. this selection process is described in the iso/iec 14443-3. the figure 118 depicts the states which a tag and a reader have to pass through to enter the protocol state. figure 118: iso14443a states for pcd and picc the selection procedure starts when a picc enters the reader field and the pcd sends a reqa (or wupa) command followed by an anticollision procedure (incl. select, rats and pps). picc states power off (no field) idle (field on) ready reqa, wupa active select rats iso 14443-4 standby pcd states poll for picc with reqa receive atqa perform bit frame anticollision loop check for sak increase cascade level uid not complete iso 14443-4 uid complete & picc compliant to iso 14443-4
AS3911B C 124 ams datasheet: 2014-jun-12 [v1-08] application information setting up AS3911B for iso 14443a anticollision to setup the AS3911B for the iso14443a anticollision following steps are to be followed: 1. the initiator operation mode of AS3911B must be setup for iso 14443a in the mode definition register (default is already for iso14443a). 2. the tx and rx bit rates must be set up to default 106kbps in the bit rate definition register . 3. set the antcl bit in the iso14443a and nfc 106kb/s settings register . this needs to be set before sending the reqa (or wupa). as a resu lt of setting this bit, the AS3911B will not trigger a fr aming error if in case the collision occurs in the atqa or during anticollision procedure. note(s): this bit must be set to one for reqa, wupa and antocollision commands, for other commands it has to be zero. 4. review and set the value for mask receive timer register less than the frame delay time as required by the iso14443a. and set the no-response timer register 1 & no-response timer register 2 according to the requirements. this is typically larger than the fdt. note(s): AS3911B offers the resolution of n/2 (64/fc - half steps) compared to n (128/fc) as mentioned in 14443a so that the receiver can be unmasked n/2 step before the actual transmission from the pic. 5. according to iso 14443a the fdt must be 1236/fc if last transmitter bit if 1 or 1172/fc if last transmitter bit is 0. as a simple rule one can follow the following. figure 119: selection of mrt & nrt for a given fdt pcd to picc fdt mrt < fdt ? 64/fc nre > fdt + 64/fc t picc to pcd
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 125 application information 6. the receiver and transmitte r operation options related to operation mode have to be defined. this is done automatically by sending the direct command analog preset . if different options are required apart from those defined by analog preset , then such options must be additionally set by writing the appropriate registers. 7. set rx_en and tx_en in the operation control register . rfid protocols usually require that the reader field is turned on for a while before sending the first command (5 ms for iso14443). general purpose timer can be used to count this time. 8. the reply form picc for the reqa, wupa and replies within anticollision sequen ce before till before sak do not contain crc. in this case the no_crc_rx bit in the auxiliary definition register must be set to 1 (receive without crc) before sending these commands. reqa and wupa sending of these two commands is simple since they are implemented as the AS3911B dire ct commands (transmit reqa and transmit wupa). the end of transmission of these commands is signaled to microcontroller by an interrupt - irq due to end of transmission). afte r the transmission is executed, the AS3911B receiver automatically starts to observe the rfi inputs to detect a transponder af ter the expiration of the mask receive timer. a s a r e s p o n s e t o r e q a ( o r w u pa ) a l l t h e p i cc i n t h e f i e l d r e s p o n d simultaneously with an atqa. a collision can occur in this state if there are picc with different uid size or has the bit frame anticollision bits set differently. hence it is important to set the antcl bit to 1. if there is any irq (except i_nre ) that AS3911B signals, the microcontroller must consider as a valid presence of tag and must proceed with the anticollision procedure. if more than one picc are expected in the field, following algorithm must be used to select multiple tags: 1. send reqa, if there was any answer continue 2. perform anticollision, and singulate one picc 3. select the found tag and send hlta to move it to halt state 4. go to 1 and repeat this procedure till all the picc are in halt state and all the uids have been extracted.
AS3911B C 126 ams datasheet: 2014-jun-12 [v1-08] application information anticollision procedure after receiving the atqa from the tags in the field, the next step is to execute the anticollision procedure to singulate the tags. the procedure mainly uses the anticollision and select commands which consist of: ? select code sel (1byte) ? number of valid bits nvb (1 byte) ? 0 to 40 data bits of uid cln according to the value of nvb the anticollision command uses standard frame which do not use crc. in this case the transmit needs to be done with direct command transmit without crc and for the receive, the no_crc_rx bit in the auxiliary definition register must be set to 1. the final select command and its response sak contains a crc, so the transmit need s to be done with command transmit with crc and before sending this command the configuration bit no_crc_rx bit in the auxiliary definition register must be set back to 0. if there are more than one picc in the field, the collision will occur when the tags reply to the sel command during anticollision when the picc reply back with their uid. this collision can occur after a complete byte (called as full byte scenario) or it can occur within a byte (called as split byte scenario). the antcl bit in iso14443a and nfc 106kb/s settings register must be set during this procedure too. as a result, AS3911B will not trigger a fram ing error. this bit is also responsible for correct timing of anticollision and correct parity extraction. note(s): it must only be set before sending an anticollision frame, reqa or wupa. this bit must not be used in any other commands. the figure 120 depicts the flowchart on how to implement the anticollision with AS3911B.
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 127 application information figure 120: flowchart for iso14443a anticollision with AS3911B 1) fill fifo with seln + nvb (0x20) 2)set register: number of transmitted bytes register 1 = 0x00 number of transmitted bytes register 2 = 0x10 1) send command: transmit without crc 2) following interrupts: i_dct i_txe i_col (if collision occurs) i_rxs i_rxe fifo is filled in with picc response i_col ? 1) read collision display register to identify how much is the valid data before the collison occured, 2) read fifo for the response from picc yes read out fifo for the valid data from the selected picc 1) fill fifo with part 1 of bit collision anticollision: seln + nvb (available from valid tag response) + received valid data +1 or 0 for the bit where the collision occured 2) set register: mention the number of received full bytes and split bits + 1 bit in: number of transmitted bytes register 1 & number of full bytes number of transmitted bytes register 2 fifo is filled in with picc response no set: no_crc_rx = 0, antcl = 0 picc sends complete uid cascade level n (n =1) send select: fill fifo with seln + nvb(0x70) + uid cln 1) send command: transmit with crc 2) following interrupts: i_dct i_txe i_rxe fifo is filled with sak uid complete? end anticollision with rats enter cascade level n+1 no yes seln=0x93 for n=1 for 4 bytes uid seln=0x95 for n=2 for 7 bytes uid seln=0x97 for n=3 for 10 bytes uid set: no_crc_rx = 1, antcl = 1 note: since spi is byte oriented, in case of split byte scenario, the invalid msb bits must be ignored when reading out the fifo for the received data. similarly, 0s must be concatenated as msb bits to complete a byte for the transmit (which will then be ignored based on register 0x1e)
AS3911B C 128 ams datasheet: 2014-jun-12 [v1-08] application information felica reader mode the general recommendation from previous chapter is valid also for felica reader mode. bit rates 212 and 424 kb/s are supported. bit rates are the same in both (reader to tag and tag to reader) directions. modulation reader to tag is am. in felica mode the felica frame format is supported. figure 121: felica frame format felica transmission in order to transmit felica frame only the payload data is put in the fifo. the number of payload bytes is defined in the number of transmitted bytes register 1 and number of transmitted bytes register 2 . preamble length is defined by bits f_p1 and f_p0 in the iso14443b and felica settings register , default value is 48 bits, but also other options are possible. transmission is triggered by sending direct command transmit with crc . first preamble is sent, followed by sync and length bytes. then payload stored in fifo is sent, transmission is terminated by two crc bytes which are calculated by the AS3911B. length byte is calculated from number of transmitted bytes. the following equation is used: length = payload length + 1 = number of transmitted bytes +1 felica reception after transmission is done the as 3911b logic starts to parse the receiver output to detect the preamble of felica tag reply. once the preamble followed by the two sync bytes is detected the length byte and payload data are put in the fifo. crc bytes are internally checked. nfcip-1 operation the AS3911B supports all nfcip-1 initiator modes and active communication target modes. all nfcip-1 bit rates (106, 212 and 424 kbit/s) are supported. preamble: 48 data bits all logical 0 sync: 2 bytes (b2 h , 4d h ) length: length byte (value= payload length + 1), the length range is from 2 to 255 payload: payload crc: 2 bytes preamble sync length payload crc
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 129 application information nfcip-1 passive communication initiator nfcip-1 passive communication is equivalent to reader (pcd) to tag (picc) communication where initiator acts as a reader and target acts as tag. the only difference is that in case of the nfcip-1 passive communication the initiator performs initial rf collision avoidance procedure at the beginning of communication. in order to act as nfcip-1 passi ve communication initiator the AS3911B has to be configured according to table below: figure 122: operation mode and bit rate setting for nfcip-1 passive communication initial set-up of the operation control register before the start of communication is the same as in case of reader to tag communication, with the exceptio n that the transmitter is not enabled by setting the tx_en bit. the direct command nfc initial field on is sent instead. this command first performs the initial rf collision avoidance with collision avoidance threshold defined in the external field detector threshold register . the timing of collision avoidance is according to nfcip-1 standard (for timing details see figure 38 ). in case collision is not detected the tx_en bit is automatically set to switch th e transmitter on. after minimum guard time t irfg the i_cat irq is sent to inform controller that the first initiator command can be send. from this point on communication is the same as in case of iso14443a (for 106 kb/s) or felica (for 242 and 424 kb/s) reader communication. in case a presence of external field is detected an i_cac irq is sent. in such case a transmi ssion should not be performed, command nfc initial field on has to be repeated as long as collision is not detected any more. initial collision avoidance is no t limited to modes supported by nfcip-1. the initial collision avoidance according to procedure described above can be performe d before any reader mode is started to avoid collision with an hf reader or an nfc device operating in proximity. support of nfcip-1transport frame format figure 123 depicts the transport frame according to nfcip-1 standard. nfcip-1 bit rate [kb/s] operation mode setting bit rate for tx [kb/s] bit rate for rx [kb/s] comment 106 iso14443a fc/128 (~106) fc/128 (~106) 212 felica fc/64 (~212) x in felica mode data rate is the same in both directions 424 felica fc/32 (~424) x
AS3911B C 130 ams datasheet: 2014-jun-12 [v1-08] application information figure 123: transport frame format according to nfcip-1 transport frame for bit rate 212 and 424 kb/s has the same format as communication frame used during initialization and sdd. this format is also used in felica protocol (see also felica reader mode ). in case of 106 kb/s the sb (start byte at f0 h ) and len (length byte) are only used in transport frame. support of transport frame for 106 kb/s nfcip-1 communication is enabled by setting bit nfc_f0 in the iso14443a and nfc 106kb/s settings register . once this bit is set and iso 1444 3a mode with bit rate 106 kb/s is configured, the behavior of th e AS3911B framing is as follows: transmission in order to transmit a transpor t frame only the transport data has to be put in fifo. the number of transport data bytes is defined in the number of transmitted bytes register 1 and number of transmitte d bytes register 2 . transmission is triggered by sending direct command transmit with crc . first start byte with value f0 h foll owed by le ngth by te are se nt. the n transport data stored in fifo is sent, transmission is terminated by two crc bytes (e1 in figure 123 ) which are calculated by the AS3911B. length byte is calculated from number of transmitted bytes. the following equation is used: length = transport data length + 1 = number of transmitted bytes +1 reception after transmission is done the as 3911b logic starts to parse the receiver output to detect the start of tag reply. once the start of communication sequence is detected the first byte (start byte with value f0 h ) is checked the length byte and transport data bytes are put in the fifo. crc bytes are internally checked. in case the start byte is not equal to f0 h the following data bytes are still put in fifo, additionally a soft framing error irq is set to indicate the start byte error. sb len cmd0 cmd1 byte 0 byte 1 byte 2 ? ? byte n e1 sb len cmd0 cmd1 byte 0 byte 1 byte 2 ? ? byte n e2 pa transport data field transport data field frame format for 106 kbps frame format for 212 kbps and 424 kbps
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 131 application information nfcip-1 active communication initiator during nfcip-1 active communicati on both, initiator and target switch on its field when transm itting and switch off its field when receiving. in order to operate as nfcip-1 active communication initiator the AS3911B has to be configured according to table below (bit targ in the mode definition register has to be 0): figure 124: operation mode and bit rate setting for nfcip-1 active communication initiator after selecting the nfcip-1 ac tive communication mode the receiver and transmitter have to be configured properly. this configuration can be done automatically by sending direct command analog preset (see analog preset on page 54 ). during nfcip-1 active comm unication the rf collision avoidance and switching on the fi eld is performed using nfc field on commands (see nfc field on commands on page 53 ), while the sending of me ssage is performed using transmit commands as in the case of reader communication. alternatively the response rf co llision avoidance sequence is started automatically when the switching off of target field is detected in case the bit nfc_ar in the mode definition register is set. when nfcip-1 mode is activated the external field detector is automatically enabled by setting bit en_fd in the auxiliary display register . the peer detection threshold is used to detect target field. during execution of nfc field on commands, the collision avoidance threshold is used. initial set-up of the operation control register before the start of communication is the same as in case of reader to tag communication with the exceptio n that the transmitter is not enabled by setting the tx_en bit. the tx_en bit and therefore switching on of the transmitter is controlled by nfc field on commands. switching off the fiel d is performed automatically after a message has been sent. the general purpose and no-response timer control register is used to define the time during which the field stays sw itched on after a message has been transmitted. nfcip-1 bit rate [kb/s] initiator operation mode setting bit rate for tx [kb/s] bit rate for rx [kb/s] comment 106 nfcip-1 active communication fc/128 (~106) x for all nfcip-1 communication, data rate is the same in both directions. 212 nfcip-1 active communication fc/64 (~212) x 424 nfcip-1 active communication fc/32 (~424) x
AS3911B C 132 ams datasheet: 2014-jun-12 [v1-08] application information in order to receive the nfcip-1 active reply only the am demodulation channel is used. due to this the receiver am channel has to be enabled. the preset done by analog preset command enables only the am demodulation channel, while pm channel is disabled to save current. in nfcip-1 active communication the nfcip-1transport frame format (see figure 123 ) is always used. due to this the iso14443a and nfc 106kb/s settings register bit nfc_f0 is set by analog preset command (see support of nfcip-1transport frame format on page 129 ). nfcip-1 active communication sequence when bit nfc_ar in the mode definition register is set (automatic response rf collision avoidance sequence). during this sequence bits nfc_n1 and nfc_n0 of the auxiliary definition register have to be 0 to produce response colli sion avoidance sequence with n=0: 1. first the direct command nfc initial field on is sent. in case no collision was detected during rf collision avoidance the field is swit ched on and an irq with i_cat flag set is sent to controller after t irfg . 2. the message, which was prepared as in case of reader to tag communication, is tr ansmitted using transmit command. 3. after the message is sent th e field is switched off. the time between the en d of the message and switching off the field is defined by the general purpose timer. (the general purpose timer ir q may be masked since controller does not need this information). 4. after switching off its fi eld the AS3911B starts the no-response timer and observes the external field detector output to detect th e switching on of the target field. in case the target field is not detected before no-response timer timeout, an irq due no-response timer expire is sent. 5. when target field is detected an irq with i_eon flag set is sent to controller and mask-receive timer is started. after the mask receive timer expires the receiver output starts to be observed to detect start of the target response. the reception proce ss goes on as in case of reader to tag communication. 6. when the external field dete ctor detects that the target has switched off its field, it sends an irq with i_eof flag set to the controller, and in case bit nfc_ar is set automatically activates th e sequence of direct command nfc response field on . in case no collision is detected during rf collision avoidance the field is switched on and an irq with i_cat flag set is sent to controller after t arfg .
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 133 application information 7. sequence loops through point 2. in case the last initiator command is sent in next sequ ence (dls_req in case of nfcip-1 protocol) the bit nfc_ar in the mode definition register has to be put to 0 to avoid switching on the initiator field after the target has switched of its field. nfcip-1 active communication target the AS3911B target mode is activated by setting bit targ in the mode definition register to 1. when target mode is activated the external field detector is automatically enabled by setting bit en_fd in the auxiliary definition register . when bit targ is set and all bits of the operation control register are set to 0, the AS3911B is in low power initial nfc target mode. in this mode the external field detector with peer detection threshold is enabled. there are two different nfc target modes implemented (defined by mode bits of the mode definition register ): the bit rate detection mode and normal mode. in the bit rate detection mode the framing logic performs automatic detection of the initiator data rate and writes it in the nfcip bit rate detection display register . in the normal mode it is supposed that the data rate defined in the bit rate definition register is used. after selecting the nfcip-1 active target mode the receiver and transmitter have to be configured properly. configuration is the same as in case of nfcip-1 active initiator mode. this configuration can be done automatically by sending direct command analog preset (see analog preset on page 54 ). nfcip-1 active communication sequence when bit nfc_ar in the mode definition register is set (automatic response rf collision avoidance sequence). during this sequence bits nfc_n1 and nfc_n0 of the auxiliary definition register have to be 0 to produce response co llision avoidance with n=0. the following sequence assumes that the AS3911B is in the low power initial nfc target mode with the bit rate detection mode selected. bit nfc_ar in the mode definition register is set (automatic response rf collision avoidance sequence). when the initiator field is detected the following sequence is executed: 1. an irq with i_eon flag set is sent to the controller. 2. the controller turns on the oscillator, regulator and receiver. mask-receive timer is started by sending direct command start mask-receive timer . after the mask receive timer expires the rece iver output starts to be observed to detect start of the initiator message. 3. once the start of initiator message is detected, an irq due to start of receive is sent, the framing logic switches on a module which automatica lly recognizes the bit rate of signal sent by the initiator. once the bit rate is recognized an irq with i_nfct flag set is sent and the bit rate is automatically loaded in the nfcip bit rate detection display register . detection of bit rate is also a condition that automati c response rf collision
AS3911B C 134 ams datasheet: 2014-jun-12 [v1-08] application information avoidance sequence is enabled). the received message is decoded and put into the fifo, irq is sent as after any received message. 4. the controller sends direct command go to normal nfc mode , to copy the content of the nfcip bit rate detection display register to the bit rate definition register and to change the nfcip-1 target mode to normal (the command go to normal mode and reading of received data can be chained). since the tx modulation type depends on bit rate, the tx modulation type also has to be corr ectly set at this point. 5. when the external field dete ctor detects that the target has switched off its field, it sends an irq with i_eof flag set to the controller, and in case bit nfc_ar is set automatically activates th e sequence of direct command nfc response field on . bits nfc_n1 and nfc_n0 of the auxiliary definition register are used to define number n of response rf collision avoidance sequence. in case no collis ion is detected during rf collision avoidance the field is switched on and an irq with i_cat flag set is sent to controller after t arfg . 6. the reply, which was prepared as in case of reader to tag communication is transmitted using transmit command. 7. after the message is sent th e field is switched off. the time between the en d of the message and switching off the field is defined in the general purpose timer. (the general purpose timer ir q may be masked since controller does not need this information). from this point on the communication with initiator loops through the following sequence (during this sequence bits nfc_n1 and nfc_n0 of the auxiliary definition register have to be 0 to produce response rf collision avoidance with n=0): 1. after switching off its field the AS3911B starts the no-response timer and observes the external field detector output to detect the switching on of the initiator field. in case the in itiator field is not detected before no-response timer timeout, an irq due no-response timer expire is sent. 2. when initiator field is detected an irq with i_eon flag set is sent to controller and mask-receive timer is started. after the mask receive timer expires the receiver output starts to be observed to detect start of the initiator response. the re ception process goes on as in case of reader to tag communication. 3. when the external field dete ctor detects that the target has switched off its field, it sends an irq with i_eof flag set to the controller, and in case bit nfc_ar is set automatically activates th e sequence of direct command nfc response field on . in case no collision is detected during rf collision avoidance the field is switched on and an irq with i_cat flag set is sent to controller after t arfg .
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 135 application information 4. the reply which was prepared as in case of reader to tag communication is transmitted using transmit command 5. after the message is sent th e field is switched off. the time between the en d of the message and switching off the field is defined in general purpose timer. in case a new command from initiator is expected the general purpose timer irq may be masked since controller does not need this information. 6. in case a new command from initiator is expected the sequence loops through point 1. in case the target reply was the last in a sequence (dls_res in case of nfcip-1 protocol) a new command from initiator is not expected. at the moment the field is switched off, a general purpose timer irq is receive d and the AS3911B is put back in the low power nfc target mode by deactivating the operation control register . nfc mode is changed back to rate detection mode by writing the mode definition register . am modulation depth: definition and calibration the AS3911B transmitter supports ook and am modulation. the choice between ook and am modulation is done by writing auxiliary definition register bit tr_am . am modulation is preset by direct command analog preset in case the following protocols are configured: ? iso14443b ?felica ? nfcip-1 212 and 424 kb/s the am modulation depth can be automatically adjusted by setting the am modulation depth control register and sending the direct command calibrate modulation depth . there is also an alternative possibility where the command calibrate modulation depth is not used and the modulated level is defined by writing the antenna driver rfo am modulated level definition register .
AS3911B C 136 ams datasheet: 2014-jun-12 [v1-08] application information am modulation depth definition using the calibrate modulation depth direct command before sending the direct command calibrate modulation depth the am modulation depth control register has to be configured in the following way: ?the bit 7 ( am_s ) has to be set to 0 to choose definition by the command calibrate modulation depth ? bits 6 to 1 (mod5 to mod0) define target am modulation depth definition of modulation depth using bits mod5 to mod0: the rfid standard documents usually define the am modulation level in form of the modulation index. the modulation index is defined by formula (a-b)/(a+b) where a is amplitude of the non-modulated carrier and b is the amplitude of the modulated carrier. the modulation index specificat ion is different for different standards. the iso14443b modulation index is typically 10% with allowed range from 8% to 14%, range from 10 to 30% is defined in the iso15693 and 8% to 30% in the felica? and nfcip-1 212 kb/s and 424 kb/s. the bits mod5 to mod0 are used to calculate the amplitude of the modulated level. the non-modulated level which was before measured by the a/d converter and stored in an 8 bit register is divided by a binary number in range from 1 to 1.98. the bits mod5 to mod0 define binary decimals of this number. example : in case of the modulation index 10% the modulated level amplitude is 1.2222 times lower than the non-modulated level. 1.2222 converted to binary and truncated to 6 decimals is 1.001110. so in order to define the modulation index 10% the bits mod5 to mod0 have to be set to 001110. the table below depicts setting of the mod bits for some often used modulation indexes. figure 125: setting of the mod bits for some often used modulation indexes modulation index [%] a/b [dec] a/b [bin] mod5???mod0 8 1.1739 1.001011 001011 10 1.2222 1.001110 001110 14 1.3256 1.010100 010100 20 1.5000 1.100000 100000 30 1.8571 1.110111 110111 33 1.9843 1.111111 111111
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 137 application information execution of direct command calibrate modulation depth: the modulation level is adjusted by increasing the rfo1 and rfo2 driver output resistance. the rfo drivers are composed of 8 binary weighted segments. usually all these segments are turned on to define the normal , non-modulated level, there is also a possibility to increase the output resistance of the non-modulated state by writing the rfo normal level definition register . before sending the direct command calibrate modulation depth the oscillator and regulators have to be turned on. when the direct command calibrate modulation depth is sent the following procedure is executed: ? the transmitter is turned on, non-modulated level is established. ? the amplitude of the non-modulated carrier level established on the inputs rfi1 and rfi2 is measured by the a/d converter and stored in the a/d converter output register . ? based on the measurement of the non-modulated level and the target modulated level defined by the bits mod5 to mod0 the target modulated level is calculated. ? the output driver control is taken over by the calibrate register . content of the calibrate register is modified using successive approximation algorithm as long as long as the measured level is equal or as close as possible to target modulated level calculated in previous step. ? final state of the calibrate register is copied in the am modulation depth display register . content of this register is used to define the am modulated level. note(s): after this calibration procedure is finished, the content of the rfo normal level definition register should not be changed. modification of this register content will change the non-modulated amplitude and therefore the ratio between the modulated and non-modulated lev el will be changed. please also note that in case the calibration of antenna resonant frequency in used, command calibrate antenna has to be run before am modulation depth adjustment. am modulation depth definition using the rfo am modulated level definition register when the bit 7 ( am_s ) of the am modulation depth control register is set to 1 the am modulated level is controlled by writing the rfo am modulated level definition register . in case setting of the modulated level is already known it is not necessary to run the calibration procedure, the modulated level can simply be defined by writing this register. it is also possible to implement calibration procedure in external controller using the rfo normal level definition register and the direct command measure amplitude . this procedure has to be used in case the target modulation depth is deeper than 33%.
AS3911B C 138 ams datasheet: 2014-jun-12 [v1-08] application information the procedure is the following: ? write the non-modulated level in the rfo normal level definition register (usually it is all 0 to have the lower possible output resistance). ? switch on the transmitter. ? send the direct command measure amplitude . read result from the a/d converter output register . ? calculate the target modula ted level from the target modulation index and result of the previous point. ? in the following iterat ions content of the rfo normal level definition register is modified, the command measure amplitude executed and result compared to the target modulated level as long as the result is not equal or as close as possible to the target modulated level. ? at the end the content of the rfo normal level definition register which results in the target modulated level is written in the rfo am modulated level definition register while the rfo normal level definition register is restored with the non-modulated definition value. antenna tuning the AS3911B comprises the building blocks which make possible checking and adjustment of the antenna lc tank resonance frequency. the AS3911B phase and amplitude detector block is used for resonance frequency checking and adjustment. in order to implement the antenna lc tank calibration tuning capacitors have to be connected between the two coil terminals to the pins trim1_3 to trim1_ 0 and trim2_3 to trim2_0. in case single driver is used only the pins trim1_3 to trim1_0 are used, pins trim2_3 to trim2_0 are left open. figure 126 depicts connection of the trim capacitors for both, single and differential driving for the simple case where the antenna lc tank is directly connected to rfo pins. the trim pins contain the hvnm os switching transistors to v ss . the on resistance of trim1_0 an d trim2_0 switch transistors, which are meant to be connected to lsb tuning capacitor is 50 typ. at 3 v vsp_d, the on resistance of other pins is binary weighted (the on resistance of trim1_3 and trim2_3 is 6.25 typ.) the breakdown voltage of the hvnmos switch transistors is 25v, which limits the maximum peak to peak voltage on lc tank in case tuning is used. during tuning procedure the resonance frequency is adjusted by connecting some of the tuning capacitors to v ss and leaving others floating. the switches of the same binary weight are d r i ve n f r o m t h e s a m e s o u r c e a n d a r e b o t h o n o r o f f ( t h e s w i t c h e s trim1_2 and trim2_2 are for example both either on or off ).
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 139 application information antenna tuning can be automatically performed by sending direct command calibrate antenna or by an algorithm implemented in external controller by performing phase and amplitude measurements and controlling the trim switches using antenna calibration control register . antenna tuning using direct command calibrate antenna in order to perform the antenna lc tank using direct command calibrate antenna binary weighted tuning capacitors have to be connected between the two coil terminals to the pins trim1_3 to trim1_0 and trim2_3 to trim2_0. during automatic procedure, started by sending the direct command calibrate antenna , the AS3911B finds position of trim switches at which the phase difference between the rfo output signal and rfi input signal is as close as possible to target phase defined in the antenna calibration target register . in case the antenna lc tank is directly connected to rfo pins (as in case of figure 126 ) there is 90 phase shift between signal on the rfo outputs and the volt age on the rfi inputs when antenna lc tank is in resonance. in case additional emc filter is inserted between rfo outputs and antenna lc tank the phase shift in case of resonance depends on additional phase shift generated by emc filter. during execution of the direct command calibrate antenna the AS3911B runs several phase measurements and changes configuration of trim pins in order to find the best possible setting. due to this the format of the antenna calibration target register is the same as the format of direct command measure phase result. the trim pin configuration which is result of the direct command calibrate antenna can be observed by reading the antenna calibration display register . this register also contains an error flag which is set in case the tuning to target phase was not possible. after the execution of direct command calibrate antenna the actual phase can be checked by sending direct command measure phase .
AS3911B C 140 ams datasheet: 2014-jun-12 [v1-08] application information figure 126: connection of tuning capacitors to the antenna lc tank in case of single (left) and differential driving (right) antenna tuning using antenna calibration control register there is also a possibility to control the position of the trim switches by writing the antenna calibration control register . when the bit trim_s of this register is se t to 1 position of the trim switches is controlled by bits tre_3 to tre_0 . using this register and performing phase and amplitude measurements (using direct commands measure phase and measure amplitude ) different tuning algorithms can be implemented in the external controller. stream mode and transparent mode standard and custom 13.56 mhz rfid reader protocols, which are not supported by the as3911 b framing, can be realized using the AS3911B afe and fr aming implemented in the external microcontroller.
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 141 application information transparent mode after sending the direct command transparent mode the external microcontroller directly controls the transmission modulator and gets the receiver output (control logic becomes transparent). the transparent mode is entered on rising edge of signal /ss after sending the command transparent mode and is maintained as long as the signal /ss is kept high. before sending the direct command transparent mode the transmitter and receiver have to be turned on, the afe has to be configured properly. while the AS3911B is in the transparent mode the afe is controlled directly through spi interface: ? transmitter modulation is controlled by pin mosi (high is modulator on) ? signal rx_on is controlled by pin sclk (high enables rssi and agc) ? output of receiver am demo dulation chain (digitized sub-carrier signal) is sent to pin miso ? output of receiver pm demodulation chain (digitized sub-carrier signal) is sent to pin irq by controlling the rx_on advanced receiver features like the rssi and agc can be used. the receiver channel selection bits are valid also in transparent mode, therefore it is possible to use only one of the two channel outputs. in case single channel is selected it is always multiplexed to miso, while irq is kept low. configuration bits related to the iso mode, framing and fifo are of course meaningless in transparent mode, all other configuration bits are respected. use of transparent mode to implement active peer to peer (nfc) communication: the framing implemented in the AS3911B supports all active modes according to the nfcip-1 specification (iso/iec 18092:2004). in case any amendments to this specification or some custom active nfc communication need to be implemented transparent mode can be used. there is no special nfc active communication transparent mode, controlling of the tx modulation and the rx is done as described above. the difference comparing to the reader transparent mode is that the emi ssion of the carrier field has to be enabled only during tx. th is is done by writing the operation control register before and after tx. since with every spi command the transparent mode is lost it has to be re-entered. in order to receive the reply in active nfc communication mode only the am demodulation channel is used. due to this the receiver am channel has to be enabled, while pm can be disabled.
AS3911B C 142 ams datasheet: 2014-jun-12 [v1-08] application information implementing active communication requires detection of external field. setting the bit en_fd in the auxiliary definition register enables the external field detector with peer detection threshold. when bit en_fd is selected and the AS3911B is in transparent mode, the external field detector output is multiplexed to pin ir q. this enables detection of external target/initiator field and performing rf collision avoidance. in case timing of the nfc field on command is correct for the nfc active protocol which is being implemented, these commands can be used in combination with the transparent mode. these commands are used to perform the rf collision avoidance, switching on the field and timing out the minimum time from switching on the field to start of transmitting the message. after getting the interru pt, the controller generates the message in the transparent mode. when bit en_fd is set and al l bits of the operation control register are set to 0 the AS3911B is in the low power nfc target mode (same as in case of setting of targ bit, (see nfcip-1 active communication target on page 133 ). in this mode initiator field is detected. after getting an irq with i_eon flag set, the controller turns on the oscillator, regulator and receiver and performs reception in the transparent mode. mifare? classic compatibility for communication with mifare? classic compliant devices the bit6 and bit7 from the register 05h can be used to enable type a custom frames. alternatively stream mode of as3911 can be used to send and receive mifare ? classic compliant or custom frames. stream mode stream mode can be used to implement protocols, where the low level framing needed for iso14443 receive coding can be used and decoded information can be put in fifo. the main advantage of this mode over the transparent mode is that timing is generated in the AS3911B therefore the external controller does not have to operate in real time. the stream mode is selected in the mode definition register , the operating options are defined in the stream mode definition register . two different modes are supported for tag to reader communication (sub-carrier and bpsk stream modes). general rule for stream mode is that the first bit sent/received is put on the lsb position of the fifo byte. after selecting the stream mode the receiver and transmitter have to be configured properly (analog preset direct command doesn't apply for stream mode). sub-carrier stream mode: this mode supports protocols where during the tag to reader communication the time periods with sub-carrier signal are interchanged with time periods without modulation (like in the iso14443a 106 kbit/s mode). in this mode the sub-carrier
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 143 application information frequency and number of sub-carrier frequency periods in one reporting period is defined. su b-carrier frequency in the range from fc/64 (212 khz) to fc/8 (1695 khz) are supported. supported number of sub-carrier frequency periods in one reporting period range from two to eight. start of receive interrupt is sent and the first data bit is put in fifo after the first reporting ti me period with sub-carrier is detected. one bit of fifo data gives information about status of input signal during one reporting period. logic 1 means that the sub-carrier was detected during reporting period, while 0 means that no modulation was detected during reporting period. end of receive is reported when no sub-carrier signal in more than eight reporting periods have been detected. figure below depicts an example for setting scf = 01b and scp = 10b. with this setting the sub-carrier frequency is set to fc/32 (424 khz) and the reporting period to four sub-carrier periods (128/fc - ~106 s). figure 127: example of sub-carrier stream mode for scf = 01b and scp = 10b bpsk stream mode: this mode supports protocols where during the tag to reader communication bpsk code is used (like in the iso14443b mode). in this mode the sub-carrier frequency and number of sub-carrier frequency periods in one reporting period is defined. sub-carrier frequency in the range from fc/16 (848 khz) to fc/4 (3390 khz) are supported. supported number of sub-carrier frequency periods in one reporting period range from one to eight. start of receive interrupt is sent and the first data bit is put in fifo after the first reporting ti me period with sub-carrier is detected. logic 0 is used for the initially detected phase, while logic 1 indicates inverted phase comparing to the initial phase. end of receive is reported when the first reporting period without sub-carrier is detected. figure below depicts an example for setting scf = 01b and scp = 01b. with this setting the sub-carrier frequency is set to fc/8 (1695 khz) and the reporting period to two sub-carrier periods (16/fc - ~1.18s). data in fifo input signal 1 32/fc 128/fc 1 0 1
AS3911B C 144 ams datasheet: 2014-jun-12 [v1-08] application information figure 128: example of bpsk stream mode for scf = 01b and scp = 01b reader to tag communication in stream mode: reader to tag communication control is the same for both stream modes. reader to tag codi ng is defined by data put in fifo. the stx bits of stream mode definition register define the tx time period during which one bit of fifo data define the status of transmitter. in case th e data bit is set to logic 0 there is no modulation, in case it is logic 1 the transmitted carrier signal is modulated according to current modulation type setting (am or ook). transmission in stream mode is started by sending direct commands transmit without crc or transmit with crc . figure below depicts an example for setting stx = 000b. with this setting the tx time period is defined to 128/fc (~9,44 s). figure 129: example of tx in stream mode for stx = 000b and ook modulation data in fifo input signal 0 8/fc 16/fc 0 1 0 data in fifo output signal 0 128/fc 0 1 0
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 145 package drawings & markings the device is available in a 32-pin qfn (5x5mm) package. figure 130: package drawings note(s) and/or footnote(s): 1. dimensioning and tolerances conform to asme y14.5m-1994 . 2. all dimensions are in millimeters. angles are in degrees. 3. co-planarity applies to the exposed heat slug as well as the terminal. 4. radius on terminal is optional. 5. n is the total number of terminals. 6. this drawing is subjec t to change without notice. figure 131: marking yywwxzz yy ww x zz @ pb-free; year manufacturing week plant identifier traceability code sublot identifier package drawings & markings symbol min nom max a 0.80 0.90 1.00 a1 0 0.02 0.05 a2 - 0.65 1.00 a3 - 0.20 ref - l 0.35 0.40 0.45 q0o 14o b 0.18 0.25 0.30 d5.00 bsc e5.00 bsc e0.50 bsc d2 3.40 3.50 3.60 e2 3.40 3.50 3.60 d1 - 4.75 bsc - e1 - 4.75 bsc - aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - n32 AS3911B yywwxzz @ green rohs
AS3911B C 146 ams datasheet: 2014-jun-12 [v1-08] ordering & contact information figure 132: ordering information buy our products or get free samples online at: www.ams.com/icdirect technical support is available at: www.ams.com/technical-support for further information and requests, e-mail us at: ams_sales@ams.com for sales offices, distributors and representatives, please visit: www.ams.com/contact headquarters ams ag tobelbaderstrasse 30 8141 unterpremstaetten austria, europe tel: +43 (0) 3136 500 0 website: www.ams.com ordering code type marking delivery form AS3911B-aqft packaged 32-pin qfn (5x5mm) AS3911B tape & reel ordering & contact information
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 147 rohs compliant & ams green statement rohs: the term rohs compliant means that ams products fully comply with current rohs directives. our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, rohs compliant products are suitable for use in specif ied lead-free processes. ams green (rohs compliant and no sb/br): ams green defines that in addition to rohs compliance, our products are free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material). important information: the information provided in this statement represents ams ag knowledge and belief as of the date that it is provided. ams ag bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are unde rway to better integrate information from third parties. ams ag has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams ag and ams ag suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. rohs compliant & ams green statement
AS3911B C 148 ams datasheet: 2014-jun-12 [v1-08] copyrights & disclaimer copyright ams ag, tobelbader strasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. devices sold by ams ag are covered by the warranty and patent indemnification provisions appe aring in its general terms of trade. ams ag makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams ag reserves the right to ch ange specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams ag for each application. this product is provided by ams ag as is and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any th ird party shall arise or flow out of ams ag rendering of technical or other services. legal notice: capacitive wakeup feature is covered by patent us6150948 (low-power radio frequency identification reader) for which ams ag is exclusive licensee including, not limited to copyrights, patents, trademarks and trade secrets related thereto. purchase of ams ics with mifare classic? compatibility: this ams ag ic offers modes to be compatible with mifare? classic rfid tags. this allows to build mifare? classic compatible reader systems. mifare? and mifare? classic are trademarks of nxp b.v., high tech campus 60 nl-5656 ag eindhoven, nl. purchase of ams mifare? classic compatible products does not provide a license of any nxp rights, in particular does not provide the right to use mifare? or mifare? classic as a tradem ark to brand such systems. copyrights & disclaimer
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 149 document status document status product status definition product preview pre-development information in this datasheet is based on product ideas in the planning phase of development. all specifications are design goals without any warranty and are subject to change without notice preliminary datasheet pre-production information in this datasheet is based on products in the design, validation or qualif ication phase of development. the performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice datasheet production information in this datashee t is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams ag standard warranty as given in the general terms of trade datasheet (discontinued) discontinued information in this datasheet is based on products which conform to specifications in accordance with the terms of ams ag standard warranty as given in the general terms of trade, but these products have been superseded and should not be used for new designs document status
AS3911B C 150 ams datasheet: 2014-jun-12 [v1-08] revision information note(s) and/or footnote(s): 1. page numbers for the previous version may di ffer from page numbers in the current revision changes from 1-07 (2014-jun-06) to current revision 1-08 (2014-jun-12) page (1) updated figure 4 4 updated figure 5 6 revision information
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 151 appendix - errata notes errata 1 i_rxs interrupt is not generated under all conditions description: due to a design error the i_rxs (end of receive) interrupt is not generated in some cases when the reception signal is noisy and receiver detect an error. workaround: to be able to develop a solid firmware routines it is recommended to check also error interrupts additionally to the i_rxs to detect the end of receive. appendix - errata notes
AS3911B C 152 ams datasheet: 2014-jun-12 [v1-08] content guide 1 general description 2 key benefits & features 3 applications 3 block diagram 4 pin assignment 6absolute maximum ratings 8 electrical characteristics 8 operating conditions 8 dc/ac characteristics for digital inputs and outputs 8 cmos inputs: 9cmos outputs: 9 electrical specification 12 detailed description 13 transmitter 13 receiver 13 phase and amplitude detector 13 a/d converter 14 capacitive sensor 14 external field detector 14 quartz crystal oscillator 14 power supply regulators 15 por and bias 15 rc oscillator and wake-up timer 15 iso14443 and nfcip-1 framing 15 fifo 15 control logic 16 spi interface 16 application information 16 operating modes 16 transmitter 18 slow transmitter ramping 18 receiver 19 demodulation stage 20 filtering and gain stages 22 digitizing stage 23 agc, squelch and rssi 24 receiver in nfcip-1 active communication mode 25 capacitive sensor 26 capacitor sensor calibration 27 wake-up mode 28 auto-averaging 29 quartz crystal oscillator 29 timers 30 mask receive timer and no-response timer 31 general purpose timer 31 wake-up timer content guide
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 153 content guide 32 a/d converter 32 phase and amplitude detector 32 phase detector 33 amplitude detector 34 external field detector 34 peer detection threshold 34 collision avoidance threshold 35 power supply system 37 vsp_rf regulator 38 vsp_a and vsp_d regulators 38 power-down support block 38 measurement of supply voltages 39 communication to external microcontroller 39 serial peripheral interface (spi) 41 writing of data to addressable registers (write mode) 42 reading of data from addressable registers (read mode) 42 loading transmitting data into fifo 43 reading received data from fifo 44 direct command mode 44 direct command chaining 45 spi timing 46 interrupt interface 47 fifo water level and fifo status registers 48 pin mcu_clk 49 direct commands 52 set default 52 clear 52 transmit commands 53 nfc field on commands 54 go to normal nfc mode 54 analog preset 56 mask receive data and unmask receive data 56 measure amplitude 56 squelch 57 reset rx gain 57 adjust regulators 58 calibrate modulation depth 58 calibrate antenna 58 measure phase 59 clear rssi 59 transparent mode 59 calibrate capacitive sensor 60 measure capacitance 60 measure power supply 60 start timers 60 test access 60 test mode entry and access to test registers
AS3911B C 154 ams datasheet: 2014-jun-12 [v1-08] content guide 62 registers 66 io configuration register 1 67 io configuration register 2 68 operation control register 69 mode definition register 70 bit rate definition register 71 iso14443a and nfc 106kb/s settings register 73 iso14443b settings register 1 74 iso14443b and felica settings register 75 stream mode definition register 77 auxiliary definition register 78 receiver configuration register 1 79 receiver configuration register 2 80 receiver configuration register 3 81 receiver configuration register 4 82 mask receive timer register 82 no-response timer register 1 83 no-response timer register 2 83 general purpose and no-response timer control register 85 general purpose timer register 1 85 general purpose timer register 2 86 mask main interrupt register 86 mask timer and nfc interrupt register 87 mask error and wake-up interrupt register 88 main interrupt register 89 timer and nfc interrupt register 90 error and wake-up interrupt register 91 fifo status register 1 92 fifo status register 2 93 collision display register 94 number of transmitted bytes register 1 94 number of transmitted bytes register 2 95 nfcip bit rate detection display register 95 a/d converter output register 96 antenna calibration control register 97 antenna calibration target register 97 antenna calibration display register 98 am modulation depth control register 99 am modulation depth display register 99 rfo am modulated level definition register 100 rfo normal level definition register 100 external field detector threshold register 103 regulator voltage control register 104 regulator and timer display register 106 rssi display register 108 gain reduction state register 109 capacitive sensor control register 110 capacitive sensor display register 110 auxiliary display register
ams datasheet: 2014-jun-12 [v1-08] AS3911B C 155 content guide 111 wake-up timer control register 112 amplitude measurement configuration register 113 amplitude measurement reference register 113 amplitude measurement auto-averaging display register 114 amplitude measurement display register 115 phase measurement configuration register 116 phase measurement reference register 116 phase measurement auto-a veraging display register 117 phase measurement display register 118 capacitance measurement configuration register 119 capacitance measurement reference register 119 capacitance measurement auto-averaging display register 120 capacitance measurement display register 120 ic identity register 121 power-up sequence 121 reader operation 122 anticollision C iso 14443a 124 setting up AS3911B for iso 14443a anticollision 125 reqa and wupa 126 anticollision procedure 128 felica reader mode 128 felica transmission 128 felica reception 128 nfcip-1 operation 129 nfcip-1 passive comm unication initiator 131 nfcip-1 active communication initiator 133 nfcip-1 active communication target 135 am modulation depth: definition and calibration 136 am modulation depth definition using the calibrate modulation depth direct command 137 am modulation depth definition using the rfo am modulated level definition register 138 antenna tuning 139 antenna tuning using direct command calibrate an- tenna 140 stream mode and transparent mode 141 transparent mode 142 mifare? classic compatibility 142 stream mode 145 package drawings & markings 146 ordering & contact information 147 rohs compliant & ams green statement 148 copyrights & disclaimer 149 document status 150 revision information 151 appendix - errata notes

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